To improve the switching characteristics and efficiency of a design, the following layout rules must be followed.
- Place the driver as close as possible to the MOSFETs.
- Place the VDD and VHB (bootstrap) capacitors as close as possible to the driver.
- Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFET but must not be in the high current path of the MOSFET(s) drain or source current.
- Use similar rules for the HS node as for GND for the high-side driver.
- Use wide traces for LO and HO closely following
the associated GND or HS traces. 60mil to 100mil width is preferable where
possible.
- Use as least two or more vias if the driver outputs or SW node must be routed from one layer to another. For GND the number of vias must be a consideration of the thermal pad requirements as well as parasitic inductance.
- Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads.
- Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can even lead to decreased reliability of the whole system.