ZHCSFS3A December 2016 – February 2019 UC1843A-SP
PRODUCTION DATA.
9.2.2.1 Oscillator
The UC1843A-SP oscillator is programmed as shown in Figure 15. Timing capacitor CT is charged from VREF (5 V) through the timing resistor RT, and discharged by an internal current source. The first step in selecting the oscillator components is to determine the required circuit dead time. Once obtained, Figure 16 is used to pinpoint the nearest standard value of CT for a given dead time. Next, the appropriate RT value is interpolated using the parameters for CT and oscillator frequency. Figure 17 shows the RT/CT combinations versus oscillator frequency. The timing resistor can be calculated from the following formula.
Figure 14. E/A Compensation Circuit for Continuous Boost and Flyback Topologies The UC1843A-SP has an internal divide-by-two flip-flop driven by the oscillator for a 50% maximum duty cycle. Therefore, their oscillators must be set to run at twice the desired power supply switching frequency.
Figure 15. Oscillator Programming 
Figure 16. Dead Time vs CT (RT > 5 kΩ) 
Figure 17. Timing Resistance vs Frequency