ZHCSKL2A December 2019 – May 2022 TUSS4470
PRODUCTION DATA
Table 7-5 lists the REG_USER registers. All register offset addresses not listed in Table 7-5 should be considered as reserved locations and the register contents should not be modified.
| Address | Acronym | Register Name | Section |
|---|---|---|---|
| 0x10 | BPF_CONFIG_1 | Bandpass filter settings | Go |
| 0x11 | BPF_CONFIG_2 | Bandpass filter settings | Go |
| 0x12 | DEV_CTRL_1 | Log-amp configuration | Go |
| 0x13 | DEV_CTRL_2 | Log-amp configuration | Go |
| 0x14 | DEV_CTRL_3 | Device Configuration | Go |
| 0x16 | VDRV_CTRL | VDRV Regulator Control | Go |
| 0x17 | ECHO_INT_CONFIG | Echo Interrupt Control | Go |
| 0x18 | ZC_CONFIG | Zero Crossing configuration | Go |
| 0x1A | BURST_PULSE | Burst pulse configuration | Go |
| 0x1B | TOF_CONFIG | Time of Flight Config | Go |
| 0x1C | DEV_STAT | Fault status bits | Go |
| 0x1D | DEVICE_ID | Device ID | Go |
| 0x1E | REV_ID | Revision ID | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-6 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
BPF_CONFIG_1 is shown in Table 7-7.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BPF_FC_TRIM_FRC | R/W | 0x0 | Override factor settings for Bandpass filter trim and control via BPF_FC_TRIM
register. Valid only when BPF_BYPASS = 0
0x0 = Factory trim 0x1 = Override Factory trim |
| 6 | BPF_BYPASS | R/W | 0x0 | Select between Bandpass filter or high pass filter
0x0 = BPF Enabled 0x1 = HPF Enabled (BPF Bypass) |
| 5:0 | BPF_HPF_FREQ | R/W | 0x0 | If BPF_BYPASS = 0: Band pass filter center frequency. See "Bandpass filter center frequency configuration" table If BPF_BYPASS = 1: High pass filter corner frequency 0x00 - 0x0F - 200kHz 0x10 - 0x1F - 400kHz 0x20 - 0x2F - 50kHz 0x30 - 0x3F - 100kHz |
BPF_CONFIG_2 is shown in Table 7-8.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R | 0x0 | Reserved |
| 5:4 | BPF_Q_SEL | R/W | 0x0 | Bandpass filter Q factor. Valid only when BPF_BYPASS = 0
0x0 = 4 0x1 = 5 0x2 = 2 0x3 = 3 |
| 3:0 | BPF_FC_TRIM | R/W | 0x0 | Offset BPF_HPF_FREQ when BPF_FC_TRIM_FRC = 1: BPF_HPF_FREQ = BPF_HPF_FREQ + BPF_FC_TRIM See "Bandpass filter center frequency range extension" table. |
DEV_CTRL_1 is shown in Table 7-9.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LOGAMP_FRC | R/W | 0x0 | Override for factory settings for LOGAMP_SLOPE_ADJ and LOGAMP_INT_ADJ |
| 6:4 | LOGAMP_SLOPE_ADJ | R/W | 0x0 | Slope or gain adjustment at the final output on VOUT pin. Slope adjustment depends on
the setting of VOUT_SCALE_SEL.
0x0 = 3.0× VOUT_SCALE_SEL+4.56×VOUT_SCALE_SEL V/V 0x1 = 3.1× VOUT_SCALE_SEL+4.71×VOUT_SCALE_SEL V/V 0x2 = 3.2× VOUT_SCALE_SEL+4.86×VOUT_SCALE_SEL V/V 0x3 = 3.3× VOUT_SCALE_SEL+5.01×VOUT_SCALE_SEL V/V 0x4 = 2.6× VOUT_SCALE_SEL+3.94×VOUT_SCALE_SEL V/V 0x5 = 2.7× VOUT_SCALE_SEL+ 4.10×VOUT_SCALE_SEL V/V 0x6 = 2.8× VOUT_SCALE_SEL+4.25×VOUT_SCALE_SEL V/V 0x7 = 2.9× VOUT_SCALE_SEL+4.4×VOUT_SCALE_SEL V/V |
| 3:0 | LOGAMP_INT_ADJ | R/W | 0x0 | Logamp Intercept adjustment. See "Logamp intercept adjustment" table in specification for values. |
DEV_CTRL_2 is shown in Table 7-10.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LOGAMP_DIS_FIRST | R/W | 0x0 | Disable first logamp stage to reduce quiescent current |
| 6 | LOGAMP_DIS_LAST | R/W | 0x0 | Disable last logamp stage quiescent current |
| 3 | RESERVED | R | 0x0 | Reserved |
| 2 | VOUT_SCALE_SEL | R/W | 0x0 | Select VOUT scaling
0x0 = Select Vout gain to map output to 3.3 V 0x1 = Select Vout gain to map output to 5.0 V |
| 1:0 | LNA_GAIN | R/W | 0x0 | Adjust LNA Gain in V/V
0x0 = 15 V/V 0x1 = 10 V/V 0x2 = 20 V/V 0x3 = 12.5 V/V |
DEV_CTRL_3 is shown in Table 7-11.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 4:2 | DRV_PLS_FLT_DT | R/W | 0x0 | Driver Pulse Fault Deglitch Time. In IO_MODE = 0 or IO_MODE = 1, DRV_PULSE_FLT will be set if start of burst is triggered and IO2 pin has not toggled for greater than deglitch Time. In IO_MODE = 2, DRV_PULSE_FLT will be set if start of burst is triggered and if IO1 or IO2 do not toggle a period longer than the deglitch time except when both pins are high. 0x0 = 64 μs 0x1 = 48 μs 0x2 = 32 μs 0x3 = 24 μs 0x4 = 16 μs 0x5 = 8 μs 0x6 = 4 μs 0x7 = Check Disabled |
| 1:0 | IO_MODE | R/W | 0x0 | Configuration for low voltage IO pins.
0x0 = IOMODE 0 0x1 = IOMODE 1 0x2 = IOMODE 2 0x3 = IOMODE 3 |
VDRV_CTRL is shown in Table 7-12.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | 0x0 | Reserved |
| 6 | DIS_VDRV_REG_LSTN | R/W | 0x0 | Automatically disable VDRV charging in listen mode every time after burst mode is
exited given VDRV_TRIGGER =0x0.
0x0 = Do not automatically disable VDRV charging 0x1 = Automatically disable VDRV charging |
| 5 | VDRV_HI_Z | R/W | 0x1 | Turn off current source between VPWR and VRDV and disable VDRV regulation.
0x0 = VDRV not Hi-Z 0x1 = VDRV in Hi-Z mode |
| 4 | VDRV_CURRENT_LEVEL | R/W | 0x0 | Pull up current at VDRV pin
0x0 = 10 mA 0x1 = 20 mA |
| 3:0 | VDRV_VOLTAGE_LEVEL | R/W | 0x0 | Regulated Voltage at VDRV pin Value is calculated as : VDRV = VDRV_VOLTAGE_LEVEL + 5 [V] |
ECHO_INT_CONFIG is shown in Table 7-13.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | RESERVED | R | 0x0 | Reserved |
| 4 | ECHO_INT_CMP_EN | R/W | 0x0 | Enable echo interrupt comparator output |
| 3:0 | ECHO_INT_THR_SEL | R/W | 0x7 | Threshold level to issue interrupt on OUT4 pin. Applied to Low pass filter output. If VOUT_SCALE_SEL=0x0 : Threshold = 0.04 x ECHO_INT_THR_SEL + 0.4 [V] If VOUT_SCALE_SEL=0x1: Threshold = 0.06 x ECHO_INT_THR_SEL + 0.6 [V] |
ZC_CONFIG is shown in Table 7-14.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ZC_CMP_EN | R/W | 0x0 | Enable Zero Cross Comparator for Frequency detection |
| 6 | ZC_EN_ECHO_INT | R/W | 0x0 | When set, provides ZC information only when object is detected |
| 5 | ZC_CMP_IN_SEL | R/W | 0x0 | Zero Comparator Input Select
0x0 = INP - VCM 0x1 = INP - INN |
| 4:3 | ZC_CMP_STG_SEL | R/W | 0x2 | Zero Cross Comparator Stage Select |
| 2:0 | ZC_CMP_HYST | R/W | 0x4 | Zero Cross Comparator Hysteresis Selection
0x0 = 30 mV 0x1 = 80 mV 0x2 = 130 mV 0x3 = 180 mV 0x4 = 230 mV 0x5 = 280 mV 0x6 = 330 mV 0x7 = 380 mV |
BURST_PULSE is shown in Table 7-15.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | HALF_BRG_MODE | R/W | 0x0 | Use output driver in half-bridge mode. When enabled, drive both high-side FET together and low-side FETs together. 0x0 = Disable half-bridge mode 0x1 = Enable half bridge mode |
| 6 | PRE_DRIVER_MODE | R/W | 0x0 | Pre-driver mode to drive external FETs
0x0 = Disable pre-driver mode 0x1 = Enable pre-driver mode |
| 5:0 | BURST_PULSE | R/W | 0x0 | Number of burst pulses. REG_VALUE=0x00 enables continuous burst mode |
TOF_CONFIG is shown in Table 7-16.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | SLEEP_MODE_EN | R/W | 0x0 | For entering or exiting sleep mode
0x0 = Wake up or exit Sleep Mode 0x1 = Enter sleep mode |
| 6 | STDBY_MODE_EN | R/W | 0x0 | For entering or exiting standby mode
0x0 = Exit Standby Mode 0x1 = Enter Standby mode |
| 5:2 | RESERVED | R | 0x0 | Reserved |
| 1 | VDRV_TRIGGER | R/W | 0x0 | Control charging of VDRV pin when DIS_VDRV_REG_LSTN = 1. This has no effect when
VDRV_HI_Z=0x1.
0x0 = Disable IVDRV 0x1 = Enable IVDRV |
| 0 | CMD_TRIGGER | R/W | 0x0 | For IO_MODE=0x0, control enabling of burst mode. Ignored for other IO_MODE values.
0x0 = Disable burst mode 0x1 = Enable burst mode |
DEV_STAT is shown in Table 7-17.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R | 0x0 | Reserved |
| 3 | VDRV_READY | R | 0x0 | VDRV pin voltage status
0x0 = VDRV is below configured voltage 0x1 = VDRV is equal or above configured voltage |
| 2 | PULSE_NUM_FLT | R | 0x0 | The Driver has not received the number of pulses defined by BURST_PULSE |
| 1 | DRV_PULSE_FLT | R | 0x0 | The Driver has been stuck in a single state in burst mode for a period longer than delgitch time set by DRV_PLS_FLT_DT |
| 0 | EE_CRC_FLT | R | 0x0 | CRC error for internal memory |
DEVICE_ID is shown in Table 7-18.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | DEVICE_ID | R | X | Device ID: 0xB9 |
REV_ID is shown in Table 7-19.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | REV_ID | R | 0x2 | Revision ID |