ZHCSI29B June 2017 – May 2019 TUSB1046A-DCI
PRODUCTION DATA.
The TUSB1046A-DCI is in GPIO configuration when I2C_EN = “0”. The TUSB1046A-DCI supports the following configurations: USB 3.1 only, 2 DisplayPort lanes + USB 3.1, or 4 DisplayPort lanes (no USB 3.1). The CTL1 pin controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.1 only, 2 lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 2. The AUXp or AUXn to SBU1 or SBU2 mapping is controlled based on Table 3.
After power-up (VCC from 0 V to 3.3 V), the TUSB1046A-DCI defaults to USB3.1 mode. The USB PD controller upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device must take TUSB1046A-DCI out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
| CTL1 PIN | CTL0 PIN | FLIP PIN | TUSB1046A-DCI CONFIGURATION | VESA DisplayPort ALT MODE
DFP_D CONFIGURATION |
|---|---|---|---|---|
| L | L | L | Power Down | — |
| L | L | H | Power Down | — |
| L | H | L | One Port USB 3.1 - No Flip | — |
| L | H | H | One Port USB 3.1 – With Flip | — |
| H | L | L | 4 Lane DP - No Flip | C and E |
| H | L | H | 4 Lane DP – With Flip | C and E |
| H | H | L | One Port USB 3.1 + 2 Lane DP- No Flip | D and F |
| H | H | H | One Port USB 3.1 + 2 Lane DP– With Flip | D and F |
| CTL1 PIN | FLIP PIN | MAPPING |
|---|---|---|
| H | L | AUXp → SBU1
AUXn → SBU2 |
| H | H | AUXp → SBU2
AUXn → SBU1 |
| L > 2 ms | X | Open |
Table 4 Details the TUSB1046A-DCI’s mux routing. This table is valid for both I2C and GPIO configuration modes.
| CTL1 PIN | CTL0 PIN | FLIP PIN | FROM | TO |
|---|---|---|---|---|
| INPUT PIN | OUTPUT PIN | |||
| L | L | L | NA | NA |
| L | L | H | NA | NA |
| L | H | L | RX1P | SSRXP |
| RX1N | SSRXN | |||
| SSTXP | TX1P | |||
| SSTXN | TX1N | |||
| L | H | H | RX2P | SSRXP |
| RX2N | SSRXN | |||
| SSTXP | TX2P | |||
| SSTXN | TX2P | |||
| H | L | L | DP0P | RX2P |
| DP0N | RX2N | |||
| DP1P | TX2P | |||
| DP1N | TX2N | |||
| DP2P | TX1P | |||
| DP2N | TX1N | |||
| DP3P | RX1P | |||
| DP3N | RX1N | |||
| H | L | H | DP0P | RX1P |
| DP0N | RX1N | |||
| DP1P | TX1P | |||
| DP1N | TX1N | |||
| DP2P | TX2P | |||
| DP2N | TX2N | |||
| DP3P | RX2P | |||
| DP3N | RX2N | |||
| H | H | L | RX1P | SSRXP |
| RX1N | SSRXN | |||
| SSTXP | TX1P | |||
| SSTXN | TX1N | |||
| DP0P | RX2P | |||
| DP0N | RX2N | |||
| DP1P | TX2P | |||
| DP1N | TX2N | |||
| H | H | H | RX2P | SSRXP |
| RX2N | SSRXN | |||
| SSTXP | TX2P | |||
| SSTXN | TX2N | |||
| DP0P | RX1P | |||
| DP0N | RX1N | |||
| DP1P | TX1P | |||
| DP1N | TX1N |