ZHCSI29B June 2017 – May 2019 TUSB1046A-DCI
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| AUXp or AUXn and SBU1 or SBU2 | ||||||
| tAUX_PD | Switch propagation delay | 400 | ps | |||
| tAUX_SW_OFF | Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE. | 500 | ns | |||
| tAUX_SW_ON | Switching time CTL1 to switch ON | 500 | ns | |||
| tAUX_INTRA | Intra-pair output skew | 100 | ps | |||
| USB3.1 and DisplayPort mode transition requirement GPIO mode | ||||||
| tGP_USB_4DP | Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa. | 4 | µs | |||
| CTL1 and HPDIN | ||||||
| tCTL1_DEBOUNCE | CTL1 and HPDIN debounce time when transitioning from H to L. | 2 | 10 | ms | ||
| I2C (Refer to Figure 11) | ||||||
| fSCL | I2C clock frequency | 1 | MHz | |||
| tBUF | Bus free time between START and STOP conditions | 0.5 | µs | |||
| tHDSTA | Hold time after repeated START condition. After this period, the first clock pulse is generated | 0.26 | µs | |||
| tLOW | Low period of the I2C clock | 0.5 | µs | |||
| tHIGH | High period of the I2C clock | 0.26 | µs | |||
| tSUSTA | Setup time for a repeated START condition | 0.26 | µs | |||
| tHDDAT | Data hold time | 0 | μs | |||
| tSUDAT | Data setup time | 50 | ns | |||
| tR | Rise time of both SDA and SCL signals | 120 | ns | |||
| tF | Fall time of both SDA and SCL signals | 20 × (V(I2C)/5.5 V) | 120 | ns | ||
| tSUSTO | Setup time for STOP condition | 0.26 | μs | |||
| Cb | Capacitive load for each bus line | 150 | pF | |||