7.3.1 Touch-Screen Operation

A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in resistance at a given point on the matrix where an input (stylus, pen, or finger) touches the screen. The change in the resistance ratio marks the location on the touch screen.

The TSC2013-Q1 device supports resistive 4-wire configurations as shown in Figure 15. The circuit determines location in two coordinate-pair dimensions, although addition of a third dimension for measuring pressure is possible.

7.3.2 4-Wire Touch Screen Measurements

Figure 15 shows construction of a typical four-wire touch screen. The screen consists of two transparent resistive layers separated by insulating spacers.

Figure 15. Four-Wire Touch Screen Construction

The four-wire touch-screen panel works by applying a voltage across the vertical or horizontal resistive network.

To determine a touch location, the TSC2013-Q1 device provides a set of eight data measurements (X1, X2, IX, Y1, Y2, IY, Z1, and Z2). Figure 17 through Figure 19 show the internal ADC configurations. Taking an X1 measurement involves activating the X+ and X– drivers and digitizing the voltage at Y+. The R_(SENSE) resistor must be connected as shown in Figure 14. The SNSGND and AUX pins connect to one end of R_(SENSE), and the other end connects to the AGND pin.

The TSC2013-Q1 device can also measure touch pressure (Z). To determine a pen or finger touch, determination of the pressure of the touch is required. Generally, having very high performance for this test is not necessary. Therefore, TI recommends 10-bit resolution mode. Several different ways of performing this measurement are available. The TSC2013-Q1 device supports two methods. The first method requires knowing the X-plate resistance, the measurement of X1, and two additional cross-panel measurements (Z2 and Z1) of the touch screen (see Figure 16). Equation 1 calculates the touch resistance (R_(TOUCH)).

Equation 1.

The second method requires knowing both the X-plate and Y-plate resistance, and the measurement of X1, Y1, and Z1. Equation 2 also calculates the touch resistance.

Equation 2.

Figure 16. Pressure Measurement

Figure 17. X-Coordinate Differential-Triplet Measurement (X1, X2, IX)

Figure 18. Y-Coordinate-Differential-Triplet Measurement (Y1, Y2, IY)

Figure 19. Z-Measurement (Z1, Z2)

When touching or pressing the touch panel with the drivers to the panel turned on, the voltage across the touch panel often overshoots and then slowly settles down (decays) to a stable DC value. This effect is a result of mechanical bouncing caused by vibration of the top-layer sheet of the touch panel when pressing the panel. Without accounting for this settling time, the converted value is in error. Therefore, introducing a delay between the time the driver for a particular measurement is turned on and the time a measurement is made is necessary.

In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (such as noise generated by the LCD panel or back-light circuitry). The value of these capacitors provides a low-pass filter to reduce noise, but causes an additional settling-time requirement when the panel is touched.

The TSC2013-Q1 device offers several solutions to this problem. A programmable delay time is available that sets the delay between turning the drivers on and making a conversion. The TSC2013-Q1 device uses this delay, referred to as the panel voltage-stabilization time, in some of the device modes. In other modes, commands can cause the TSC2013-Q1 device to turn on the drivers only without performing a conversion. Issuing the command to perform a conversion occurs after allowing sufficient stabilization time.

The TSC2013-Q1 touch-screen interface can measure different data sets. Determination of these measurements is possible under three different modes of the ADC:

• TSMode1: conversion controlled by the TSC2013-Q1 device and initiated by the touchscreen controller (TSC)
• TSMode2: conversion controlled by the TSC2013-Q1 device and initiated by the host responding to the PENIRQ signal
• TSMode3: conversion completely controlled by the host processor

7.3.3 Analog-to-Digital Converter

Figure 20 shows the analog inputs of the TSC2013-Q1 device. A multipexer provides the analog inputs (X, Y, and Z touch panel coordinates and auxiliary inputs) to the successive-approximation register (SAR) analog-to-digital converter (ADC). The basis of ADC architecture is capacitive redistribution architecture, which inherently includes a sample-and-hold function.

1. Untrimmed resistor; see the typical value in the table.

Figure 20. Simplified Diagram of the Analog Input Section

A unique configuration of low on-resistance switches allows an unselected ADC input channel to provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input to the converter and a differential reference input architecture, negating errors caused by the on-resistance of the driver switches is possible.

Two ADC-control registers control the ADC. Several modes of operation are possible, depending on the bits set in the control registers. Programming of channel selection, scan operation, preprocessing, resolution, and conversion rate is through these registers. The following sections outline these modes for each type of analog input. The appropriate result register stores the conversion results.

7.3.3.1 Data Format

The TSC2013-Q1 output data are in straight binary format as shown in Figure 21. Figure 21 shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise.

1. Reference voltage at converter: +REF – (–REF). See Figure 20.

2. Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 20.

Figure 21. Ideal Input Voltages and Output Codes

7.3.3.5 Touch Detect

The PINTDAV pin can be programmed to generate an interrupt to the host. Figure 22 shows an example for a typical screen-touch situation. While in the power-down mode, the Y– driver is on and connects to GND. The internal pen-touch signal depends on whether or not the X+ input is low. A touch on the panel pulls the X+ input to ground through the touch screen and sets the internal pen-touch output to low because of the detection on the current path through the panel to ground, which initiates an interrupt to the processor. During the measurement cycles for X and Y-position, the device disconnects the X+ input, which eliminates any leakage current from the pullup resistor flowing through the touch screen, thus causing no errors.

1. Untrimmed resistor; see the typical value in the table.

Figure 22. Example of a Pen-Touch Induced Interrupt via the PINTDAV Pin

In modes where the TSC2013-Q1 device must detect whether or not a touch remains on the screen (for example, when doing a pen-touch-initiated X, Y, and Z conversion), the TSC2013-Q1 device must reset the drivers to connect the R_(IRQ) resistor again. Because of the high value of this pullup resistor, any capacitance on the touch screen inputs causes a long delay time, and may prevent the detection from occurring correctly. To prevent this possible delay, the TSC2013-Q1 device has a circuit that allows prechargingd any screen capacitance, so that the pullup resistor must not be the only source for the charging current. The setting for the time allowed for this precharge, as well as the time needed to sense if the screen touch remains, is in the configuration register.

This configuration underscores the need to use the minimum possible capacitor values on the touch-screen inputs. Capacitors can be used to reduce noise, but capacitors with too large a value increase the required precharge and sense times, as well as the panel voltage-stabilization time.

7.3.3.6 Preprocessing

The TSC2013-Q1 device offers an array of powerful preprocessing operations that reduce unnecessary traffic on the bus and reduce the host processor loading. This reduction is especially critical for the serial interface because of the slow bus speed and the high CPU bandwidth required for I²C communication.

All data-acquisition tasks are looking for specific data that meet certain criteria. Many of these tasks fall into a predefined range, while other tasks may be looking for a value in a noisy environment. If the host processor is to retrieve all these data for processing, the limited bus bandwidth quickly saturates, along with the host processor processing capability. In any case, reserving the host processor for more critical tasks rather than routine work is always necessary.

The preprocessing unit consists of two main functions which result in the combined MAV (median and averaging-value) filter: the median value filter (MVF) and the averaging-value filter (AVF).

7.3.3.6.1 Preprocessing—Median Value Filter and Averaging Value Filter

The first preprocessing function, a combined MAV filter, can operate independently as a median value filter (MVF), an averaging value filter (AVF), and a combined filter (MAV filter).

If the acquired signal source is noisy because of the digital switching circuit, evaluating the data without noise may be necessary. In this case, the median value filter (MVF) operation helps to discard noise. The first action is sorting the array of N converted results. The return value is either the middle (median value) of an array of M converted results, or the average value of a window size of W of converted results:

N= the total number of converted results used by the MAV filter

M= the median value filter size programmed

W= the averaging window size programmed

If M is equal to 1, then N is equal to W. A special case is W equal to 1, which indicates a bypassed MAV filter. Otherwise, if W is greater than 1, averaging is the only function performed on these converted results. In either case, the return value is the averaged value of window size W of converted results.

If M is greater than 1 and W is equal to 1, then N is equal to M, meaning the only operating filter is the median value filter. The return value is the middle position converted result from the array of M converted results.

If M is greater than 1 and W is greater than 1, then N is equal to M. In this case, W is less than M. The return value is the averaged value of middle portion W of converted results out of the array of M converted results. Because the value of W is an odd number in this case, the calculation of the averaging value counts the middle-position converted result twice (averaging a total of W + 1 converted results).

Table 1. Median Value Filter-Size Selection

M1	M0	MEDIAN VALUE FILTER M =	POSSIBLE AVERAGING WINDOW SIZE W =
0	0	1	1, 4, 8, 16
0	1	3	1
1	0	7	1, 3
1	1	15	1, 3, 7

Table 2. Averaging Value Filter-Size Selection

		AVERAGING VALUE FILTER SIZE SELECTION W =
W1	W0	M = 1 (Averaging Only)	M > 1
0	0	1	1
0	1	4	3
1	0	8	7
1	1	16	Reserved

The device uses the default MVF setting (median value filter with averaging bypassed) for any invalid MAV filter configuration. For example, if M1, M0, W1, and W0 equals 1, 0, 1, and 0 (respectively), the MAV filter will perform as if it were configured for 1, 0, 0, 0, median filter only with filter size of 7, and no averaging. The only exception is when M is greater than 1 and when W1 and W0 equal 1. Avoid using this reserved setting.

Table 3. Combined MAV Filter Setting

M	W	INTERPRETATION	N =	OUTPUT
= 1	= 1	Bypass both MAF and AVF	W	The converted result
= 1	> 1	Bypass MVF only	W	Average of W converted results
> 1	= 1	Bypass AVF only	M	Median of M converted results
> 1	> 1	M > W	M	Average of middle W of M converted results with the median counted twice

The MAV filter is available for all analog inputs including the touch-screen inputs and the AUX measurement.

Figure 23. MAV Filter Operation

7.4.1 Conversion Controlled by TSC2013-Q1 and Initiated by TSC2013-Q1 (TSMode 1)

In TSMode 1, before a pen-touch detection is possible, the TSC2013-Q1 device must be programmed with the PSM bit set to 1 and one of two scan modes:

1. X-triplet, Y-triplet, Z-scan (converter function select bits C[3:0] = control byte 1 D[6:3] = 0000)
2. IX-IY scan (converter function select bits C[3:0] = control byte 1 D[6:3] = 0001).

See Table 7 for more information on the converter function-select bits.

On touching the touch panel, the internal pen-touch signal activates, lowering the PINTDAV output if programmed as PENIRQ. The TSC2013-Q1 device then executes the preprogrammed scan function without a host intervention.

7.4.1.1 IX-IY Scan

The TSC2013-Q1 device starts up the internal clock. The device then turns on the Y-drivers, and after a programmed panel voltage-stabilization time, the device powers up the ADC and converts the IY coordinate. With preprocessing selected, several conversions can occur. When data preprocessing is complete, a temporary register stores the IY coordinate result.

If the screen touch remains at this time, the device enables the X-drivers and the process repeats but measures the IX coordinate instead, storing the result in a temporary register.

Figure 24 shows a flowchart for this process. The time required to go through this process depends on the selected resolution, internal conversion clock rate, panel voltage-stabilization time, precharge and sense times, and the selection status of preprocessing. Use Equation 3 to calculate the time required to achieve a complete X and Y coordinate (sample set) reading.

Equation 3.

where

• t_(COORDINATE) = time to complete IX and IY coordinate reading
• N = number of measurements for MAV filter input, as given in Table 3 as N
  (For no MAV: M1 = M0 = W1 = W0 = 0)
• t_(PVS) = panel voltage stabilization time, as listed in Table 11
• t_(PRE) = precharge time, as listed in Table 11
• t_(SNS) = sense time, as listed in Table 11
• B = number of bits of resolution
• ƒ_(OSC) = TSC onboard OSC clock frequency. See the Electrical Characteristics section for supply frequency (SNSVDD)
• ƒ_(ADC) = ADC clock frequency, as listed in Table 11
• t_(OH1) = overhead time number 1 = 2.5 internal clock cycles
• t_d(OH1) = total overhead time for t_(PVS), t_(PRE), and t_(SNS) = 10 internal clock cycles
• t_c(OH) = total overhead time for A-to-D conversion = 3 internal clock cycles
• t_(PPRO) = preprocessor preprocessing time as listed in Table 4

Table 4. Preprocessing Delay

		t(PPRO) =
M =	W =	FOR B = 12 BIT	FOR B = 10 BIT
1	1, 4, 8, 16	2	2
3, 7	1	28	24
7	3	31	27
15	1	31	29
15	3	34	32
15	7	38	36

Figure 24. Example of an IX and IY Touch-Screen Scan Using TSMode 1

7.4.1.2 X-Triplet, Y-Triplet, Z-Scan

The TSC2013-Q1 device starts up the internal clock. The device then turns on the Y-drivers, and after a programmed panel voltage-stabilization time, powers up the ADC and converts the Y-triplet. With preprocessing selected, several conversions can occur. When data preprocessing is complete, temporary registers store the Y-triplet results.

If the screen touch remains at this time, the device enables the X-drivers and the process repeats but measures the X-triplet instead, storing the result in temporary registers.

The process continues in the same way, but measures the Z1 and Z2 values instead, storing the results in temporary registers. When the complete sample set of data (X1, X2, IX, Y1, Y2, IY, Z1, and Z2) are available, the device loads the data in the X1, X2, IX, Y1, Y2, IY, Z1, and Z2 registers. Figure 25 shows this process. This process time depends on the previously described settings. Use Equation 4 to calculate the time for a complete X1, X2, IX, Y1, Y2, IY, Z1, and Z2 coordinate reading.

Equation 4.

where

• t_(OH2) = overhead time number 2 = 3.5 internal clock cycles

Figure 25. Example of an X-Triplet and Y-Triplet Coordinate Touch-Screen Scan Using TSMode 1

7.4.2 Conversion Controlled by TSC2013-Q1 and Initiated by Host (TSMode 2)

In TSMode 2, the TSC2013-Q1 device detects when a touch of the touch panel occurs and causes the internal pen-touch signal to activate, which lowers the PINTDAV output if programmed as PENIRQ. The host recognizes the interrupt request and then writes to the ADC control register to select one of the following two Touch-Screen Scan functions:

1. X-triplet, Y-triplet, Z-scan (converter function select bits C[3:0] = control byte 1 D[6:3] = 0000); or
2. IX-IY scan (converter function select bits C[3:0] = control byte 1 D[6:3] = 0001).

See Table 7 for more information on the converter function-select bits.

The conversion process then proceeds as shown in Figure 26. See the IX-IY Scan and X-Triplet, Y-Triplet, Z-Scan sections for additional details.

The main difference between this mode and the previous mode is that the host, not the TSC2013-Q1 device, decides when the touch-screen scan begins.

Use Equation 3 to calculate the time required to convert both IX and IY under host control (not including the time required to send the command over the I²C bus):

Figure 26. Example of an IX and IY Touch-Screen Scan Using TSMode 2

7.4.3 Conversion Controlled by Host (TSMode 3)

In TSMode 3, the TSC2013-Q1 device detects a touch of the touch panel and causes the internal pen-touch signal to be active, which lowers the PINTDAV output if programmed as PENIRQ. The host recognizes the interrupt request. Instead of starting a sequence in the TSC2013-Q1 device, which then reads each coordinate in turn, the host must now control all aspects of the conversion. Generally, on receiving the interrupt request, the host turns on the X drivers.

After waiting for the settling time, the host then addresses the TSC2013-Q1 device again, this time requesting an X-coordinate conversion.

The process then repeats for the Y and Z coordinates. Figure 27 and Figure 29 show this process. Figure 27 shows two consecutive scans on IX and IY. Figure 29 shows a single Z scan.

Use Equation 5 to calculate the time required to convert any single X-triplet or Y-triplet under host control (not including the time required to send the command over the I²C bus):

Equation 5.

where

• t_d(OH2) = total overhead time for t_(PRE) and t_(SNS) = 6 internal clock cycles

1. Optional. If not turned on, it will be turned on by the scan mode, when detected.

Figure 27. Example of X-Triplet and Y-Triplet Touch-Screen Scan
(Without Panel Stabilization Time) Using TSMode 3

Use Equation 6 to calculate the time required to convert any single X-triplet or Y-triplet under host control (not including the time required to send the command over the I²C bus):

Equation 6.

Figure 28. Example of a Single X-Triplet Touch-Screen Scan
(With Panel Stabilization Time) Using TSMode 3

Use Equation 7 to calculate the time required to convert any Z1 and Z2 coordinate under host control (not including the time required to send the command over the I²C bus):

Equation 7.

1. Optional. If not turned on, it will be turned on by the scan mode, when detected.

Figure 29. Example of Z1 and Z2 Coordinate Touch-Screen Scan
(Without Panel Stabilization Time) Using TSMode 3

If the drivers do not turn on prior to programming the touch-screen scan mode, include the panel stabilization time. In this case, use Equation 8 to calculate the time required to convert any single X or Y under host control (not including the time required to send the command over the I²C bus):

Equation 8.

Figure 30. Example of a Z1 and Z2 Coordinate Touch-Screen Scan
(With Panel Stabilization Time) Using TSMode 3

7.5.1 I²C Interface

The TSC2013-Q1 device supports the I²C serial bus and data transmission protocol in all three defined modes: standard, fast, and high-speed. A device that sends data onto the bus has the definition of a transmitter, and a device receiving data that of a receiver. The device that controls the message is a master. Devices controlled by the master are slaves. A master device that generates the serial clock (SCL), controls bus access, and generates the START and STOP conditions must control the bus The TSC2013-Q1 device operates as a slave on the I²C bus. Connections to the bus are through the open-drain I/O lines, SDA and SCL.

The following bus protocol has been defined (see Figure 31):

• A device can initiate data transfer only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals.

Accordingly, definitions for the following bus conditions follow:

Figure 31 shows the data-transfer process on the I²C bus. Depending on the state of the R/W bit, two types of data transfer are possible:

1. Data transfer from a master transmitter to a slave receiver.

The first byte transmitted by the master is the slave address. A number of data bytes occurs next. The slave returns an acknowledge bit after the slave address and each received byte.

2. Data transfer from a slave transmitter to a master receiver.

The master transmits the first byte, the slave address. The slave then returns an acknowledge bit. Next, the slave transmits a number of data bytes to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, the master returns a not-acknowledge.

The master device generates all of the serial clock pulses and the start and stop conditions. A transfer ends with a stop condition or a repeated start condition. Because a repeated start condition is also the beginning of the next serial transfer, the bus is not released.

The TSC2013-Q1 device can operate in the following two modes:

1. Slave receiver mode

Reception of serial data and clock is through SDA and SCL. After the reception of each byte, the receiver transmits an acknowledge bit. Start and stop conditions designate the beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave address and direction bit.

2. Slave transmitter mode

Reception and handling of the first byte (the slave address) is the same as in the slave receiver mode. However, in this mode the direction bit indicates a reversal of the transfer direction. Serial data transmission on SDA by the TSC2013-Q1 device occurs during input of the serial clock on SCL. Start and stop conditions designate the beginning and end of a serial transfer.

7.5.1.1 I²C Fast or Standard Mode (F-S Mode)

In I²C fast or standard (F-S) mode, serial data transfer must meet the timing shown in the timing requirement tables in the Specifications section.

In the serial transfer format of F-S mode, the master signals the beginning of a transmission to a slave with a start condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has finished communicating with the slave, the master issues a stop condition (P), which is a low-to-high transition on SDA while SCL is high, as shown in Figure 31. The bus is free for another transmission after the occurrence of a stop. Figure 31 shows the complete F-S mode transfer on the I²C, two-wire serial interface. Transmission of the address byte, control byte, and data byte is between the start and stop conditions. The SDA state can only change while SCL is low, except for the start and stop conditions. Data transmission is in 8-bit words. Nine clock cycles are necessary to transfer the data into or out of the device (8-bit word plus acknowledge bit).

Figure 31. Complete Fast or Standard-Mode Transfer

7.5.1.2 I²C High-Speed Mode (Hs Mode)

Serial data transfer format in high-speed (Hs) mode meets the fast or standard (F-S) mode I²C bus specification. Hs mode can only commence after the following conditions (all of which are in F-S mode) exist:

1. Start condition (S)
2. 8-bit master code (0000 1xxx)
3. Not-acknowledge bit (N)

Figure 32 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for triggering Hs mode. Do not use these codes for slave addressing or any other purpose. The master code indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the Hs mode specification. Because no device can acknowledge the master code, a not-acknowledge bit (N) follows the master code.

After the not-acknowledge bit (N) and SCL achieve a high level, the master switches to Hs-mode and enables (at time t_(H); shown in Figure 32) the current-source pullup circuit for SCL. Because other devices can delay the serial transfer before t_(H) by stretching the LOW period of SCL, the master enables the current-source pullup circuit when all devices have released SCL and SCL has reached a high level, thus speeding up the last part of the rise time of the SCL.

The master then sends a repeated start condition (Sr) followed by a 7-bit slave address with an R/W bit address, and receives an acknowledge bit (A) from the selected slave. After a repeated start (Sr) condition and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables the current-source pullup circuit. This disabling enables other devices to delay the serial transfer by stretching the low period of SCL. The master re-enables the current-source pullup circuit again when all devices have released, and SCL reaches a high level, which speeds up the last part of the SCL signal rise time.

Data transfer continues in Hs mode after the next repeated start (Sr), and only switches back to F-S mode after a stop condition (P). To reduce the overhead of the master code, the master can link to a number of Hs mode transfers, separated by repeated start conditions (Sr).

Figure 32. Complete High-Speed Mode Transfer

7.5.2 Digital Interface

7.5.2.1 Address Byte

The TSC2013-Q1 device has a 7-bit slave address word. The factory presets the first five bits (MSBs) of the slave address to comply with the I²C standard for ADCs; the setting is always 1 0010. The logic state of the address input pins (AD1 through AD0) determines the two LSBs of the device address to activate communication. Therefore, one bus can accommodate a maximum of four devices with the same preset code at one time.

The device only reads the AD1 through AD0 address inputs during a power-up of the device, and the pin connections should be to a digital supply (I/OVDD) or digital ground (DGND). The TSC2013-Q1 latches the slave address on the falling edge of SCL after reception of the R/W bit by the slave.

The last bit of the address byte (R/W) defines the operation to be performed. Setting the bit to 1 selects a read operation. Setting the bit to 0 selects a write operation. Following the start condition, the TSC2013-Q1 device monitors the SDA bus, checking the transmitted device-type identifier. On receiving the 1 0010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.

Table 5. I²C Slave Address Byte

MSB D7	D6	D5	D4	D3	D2	D1	LSB D0
1	0	0	1	0	AD1	AD0	R/W

R/W (D0)

1: I2C master read from TSC (I2C read addressing). 0: I2C master write to TSC (I2C write addressing).

Figure 33. I²C Bus Addressing (Slave-Address Byte Format)

7.5.3 Control Byte

7.5.4 Start a Write Cycle

A write cycle begins when the master issues the slave address to the TSC2013-Q1 device. The slave address consists of seven address bits and a write bit (R/W = 0; see Table 6).On receipt of the eighth bit, if the address matches the AD1 through AD0 address input pin setting, the TSC2013-Q1 device issues an acknowledge bit by pulling SDA low for one additional clock cycle (ACK = 0); see Figure 33.

When the master receives the acknowledge bit from the TSC2013-Q1 device, the master writes the input control byte to the slave (see Table 6). After the control byte is received by the slave, the slave issues another acknowledge bit by pulling SDA low for one clock cycle (ACK = 0). The master then ends the write cycle by issuing a STOP or repeated START condition; see Figure 34.

1. In order to start the next sequence, a stop condition must be followed by a start condition. If no stop is used, then a repeated start (Sr) must be used. Also note that if a stop condition is issued in high-speed mode, the mode reverts to the previous mode which is either fast or standard mode.

2. mh is a hexadecimal number.

Figure 34. Write Cycle

7.5.5 Register Access

Data access begins with the master issuing a START (or repeated START) condition followed by the 7-bit address and a read bit (R/W = 1; see Table 6). On receipt of the eighth bit has been received and an address match, the slave issues an acknowledge by pulling SDA low for one clock cycle (ACK = 0). The first byte of serial data then follows. After the slave has sent the first byte, it then releases the SDA line for the master to issue an acknowledge (ACK = 0). The slave issues the second byte of serial data on receiving the acknowledgment from the master (D7–D0), followed by a not-acknowledge bit (ACK = 1) from the master to indicate receipt of the last data byte has been received. The master then issues a STOP condition (P) or repeated START (Sr), which ends the read cycle, as shown in Figure 35 and Figure 36. If the master issues a not-acknowledge (ACK = 1) after receipt of the first data byte, the master must then issue a stop condition (P) to reset the registers. If the master is not ready to receive the second data byte, it should issue the acknowledge (ACK = 0), or the master should stretch the clock. On restart of the clock, the master can receive the second byte of data.

1. In order to start the next sequence, a Stop condition must be followed by a start condition. If no stop is used, then a repeated start must be used. Also note that if a stop condition is issued in high-speed mode, the mode reverts to the previous mode which is either fast or standard mode.

2. mh is a hexadecimal number.

3. If (m+n)h is greater than Fh, then (m + n)h is modulo 16.

Figure 35. Sequential Read Cycle

1. In order to start the next sequence, a Stop condition must be followed by a start condition. If no stop is used, then a repeated start must be used. Also note that if a stop condition is issued in high-speed mode, the mode reverts to the previous mode which is either fast or standard mode.

2. mh is a hexadecimal number.

Figure 36. Repeated Read Cycle

7.5.6 Communication Protocol

All control of the TSC2013-Q1 is through registers. Reading and writing to these registers are accomplished by the use of Control Byte 0, which includes a 4-bit address plus one read-write TSC register-control bit. The data registers defined in Table 9 are all 16-bit, right-adjusted.

See the Configuration and Status Registers section for the register field descriptions.

7.5.7 Register Reset

The TSC2013-Q1 device can be reset in one of three ways. First, at power-on, a power-good signal generates a prolonged reset pulse internally to all registers.

Second, an external pin, RESET, is available to perform a system reset or allow other peripherals (such as a display) to reset the device if the pulse meets the timing requirement (at least 10 μs in duration). Any RESET pulse less than 5 μs is rejected. To accommodate the timing drift between devices because of process variation, a RESET pulse duration between 5 μs and 10 μs falls into the gray area that is unrecognized, giving an undetermined result; avoid this situation. See Figure 37 for details. A good reset pulse must be low for at least 10 μs. An internal spike filter is available to reject spikes up to 20 ns wide.

See the timing requirement tables in the Specifications section for more information.

Figure 37. External Reset Timing

Third, a software reset is activated by writing a 1 to CB1.1 (bit 1 of control byte 1). Note that this reset is not self-clearing, so the user must write a 0 to remove the software reset.

A reset clears all registers and loads default values. A power-on reset and external (hardware) reset take precedence over a software reset. If the user does not clear a software reset, either a power-on reset or an external (hardware) reset clears it.

Table 10. Register Content and Reset Values⁽¹⁾

7.6.1 Configuration and Status Registers

7.6.2 Data Registers

The data registers of the TSC2013-Q1 hold data results from conversions. All of these registers default to 0000h on reset.