ZHCS761F December 2011 – May 2017 TRF7962A
PRODUCTION DATA.
Table 4-1 describes the signals.
| TERMINAL | TYPE (1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | VDD_A | OUT | Internal regulated supply (2.7 V to 3.4 V) for analog circuitry |
| 2 | VIN | SUP | External supply input to chip (2.7 V to 5.5 V) |
| 3 | VDD_RF | OUT | Internal regulated supply (2.7 V to 5 V); normally connected to VDD_PA (pin 4) |
| 4 | VDD_PA | INP | Supply for PA; normally connected externally to VDD_RF (pin 3) |
| 5 | TX_OUT | OUT | RF output (selectable output power: 100 mW or 200 mW, with VDD = 5 V) |
| 6 | VSS_PA | SUP | Negative supply for PA; normally connected to circuit ground |
| 7 | VSS_RX | SUP | Negative supply for receive inputs; normally connected to circuit ground |
| 8 | RX_IN1 | INP | Main receive input |
| 9 | RX_IN2 | INP | Auxiliary receive input |
| 10 | VSS | SUP | Chip substrate ground |
| 11 | BAND_GAP | OUT | Bandgap voltage (VBG = 1.6 V); internal analog voltage reference |
| 12 | ASK/OOK | BID | Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for direct mode 0 and 1. It can be configured as an output to provide the received analog signal output. |
| 13 | IRQ | OUT | Interrupt request |
| 14 | MOD | INP | External data modulation input for direct mode 0 or 1 |
| OUT | Subcarrier digital data output (see register 0x1A and 0x1B definitions) | ||
| 15 | VSS_A | SUP | Negative supply for internal analog circuits. Connected to GND. |
| 16 | VDD_I/O | INP | Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded. |
| 17 | I/O_0 | BID | I/O pin for parallel communication |
| 18 | I/O_1 | BID | I/O pin for parallel communication |
| 19 | I/O_2 | BID | I/O pin for parallel communication |
| 20 | I/O_3 | BID | I/O pin for parallel communication |
| 21 | I/O_4 | BID | I/O pin for parallel communication Slave select signal in SPI mode |
| 22 | I/O_5 | BID | I/O pin for parallel communication Data clock output in direct mode 1 |
| 23 | I/O_6 | BID | I/O pin for parallel communication MISO for serial communication (SPI) Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0 |
| 24 | I/O_7 | BID | I/O pin for parallel communication. MOSI for serial communication (SPI) |
| 25 | EN2 | INP | Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power down mode 2 (for example, to supply the MCU). |
| 26 | DATA_CLK | INP | Data clock input for MCU communication (parallel and serial) |
| 27 | SYS_CLK | OUT | If EN = 1 (EN2 = don't care) the system clock for the MCU is configured with register 0x09 (off, 3.39 MHz, 6.78 MHz, or 13.56 MHz). If EN = 0 and EN2 = 1, the system clock is set to 60 kHz. |
| 28 | EN | INP | Chip enable input (if EN = 0, then the chip is in sleep or power-down mode) |
| 29 | VSS_D | SUP | Negative supply for internal digital circuits |
| 30 | OSC_OUT | OUT | Crystal or oscillator output |
| 31 | OSC_IN | INP | Crystal or oscillator input |
| 32 | VDD_X | OUT | Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, an MCU) |
| PAD | PAD | SUP | Chip substrate ground |