8.3.1 RF Output

The RF output is single ended and can drive a 50-Ω load. It can be tuned with the use of an output matching network to optimize the linearity and return loss performance within a selected band.

8.3.2 Baseband Inputs

The baseband inputs consist of the in-phase signal (I) and the quadrature-phase signals (Q). These I and Q signals are differential. The baseband lines are nominally biased at 0.25-V common-mode voltage (V_CM); however, the device can operate with a V_CM in the range of 0 V to 0.5 V. The baseband input lines are normally terminated externally 50 Ω on TRF3722 evaluation board, though it is possible to modify this value if necessary to match to an external filter load impedance requirement.

8.3.3 LO Output

The LO outputs are open collector differential outputs and are biased externally. These differential outputs can be tuned to optimized output power along with OUTBUF_BIAS register settings. It also is possible to use LO outputs in single ended mode.

8.3.4 PLL Architecture

Figure 132 illustrates a block diagram of the PLL architecture.

The VCO output frequency (f_VCO) is given by Equation 1:

Equation 1.

Equation 2.

Equation 3.

Equation 4.

Where f_REF is the reference input frequency, RDIV is the reference divider division ratio and the phase - frequency detector frequency is f_PFD. PLL_DIV_SEL controls the division ratio of the programmable divider (PLL DIV) before the dual-modulus prescaler (DMP). NINT and NFRAC/2²⁵ is the integer and fractional part of the fractional divider (N.f), respectively. In Integer mode, the fractional setting is ignored and Equation 5 is applied.

Equation 5.

The complete feedback divider block consists of a PLL DIV, DMP, and N.f. The prescaler can be programmed as either a 4/5 or an 8/9. N.f includes an A and M digital counters.

Figure 132. PLL Architecture

8.3.5 External VCO

An external LO or VCO signal may be applied. If an external LO is used the internal PLL can be powered down. Alternatively, dividers, phase-frequency detector, and charge pump can remain enabled and may be used to control the V_TUNE of an external VCO. EN_EXTVCO is used to select the internal or external VCO.

8.3.6 Loop Filter

Loop filter design is critical for achieving low closed loop phase noise. Complete modulator performance data has been measured using integer mode loop filter. The integer mode loop filter was designed considering loop bandwidth 40 kHz and f_PFD 2.56 MHz. Phase margin of 60 degrees was considered. Refer to TRF3722EVM User’s Guide to obtain the details on TRF3722 loop component calculations. Figure 133 shows integer loop filter.

Figure 133. Integer Loop Filter

Frac-N performance data is obtained using the fractional loop filter shown in Figure 134. 40 kHz loop bandwidth and 15.36 MHz PFD was considered.

Figure 134. Fractional Loop Filter

8.3.7 Lock Detect

The lock detect signal is generated in the phase frequency detector by comparing the two input signals. When the two compared phase signals remain aligned for several clock cycles, an internal signal goes high. The precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged and compared against a reference voltage to generate the lock detect (LD) signal. The number of averages used is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO frequency is not locked, LD may pulse high or exhibit periodic behavior.

By default, the internal lock detect signal is made available on the LD terminal. Register bits MUX_CTRL can be used to control a multiplexer to output other diagnostic signals on the LD output.

8.4.1 Selecting PLL Divider Values

With reference to the PLL architecture illustrated in Figure 132, operation of the PLL requires TX_DIV_SEL / LO_DIV_SEL, PLL_DIV_SEL, RDIV, NINT, NFRAC and PRSC_SEL bits to be calculated.

1. TX_DIV_SEL / LO_DIV_SEL

The LO to the integrated modulator (ƒ_TX) and additional LO output (ƒ_LO) frequency is related to f_VCO according to the following:

ƒ_TX = f_VCO / TX DIV

ƒ_LO = f_VCO / LO DIV

Where TX DIV and LO DIV are related to TX_DIV_SEL and LO_DIV_SEL as:

TX_DIV_SEL / LO_DIV_SEL	TX_DIV / LO_DIV	FREQUENCY RANGE
TX_DIV_SEL = 0	TX DIV = 1	2050 MHz ≤ ƒTX ≤ 4100 MHz
TX_DIV_SEL = 1	TX DIV = 2	1025 MHz ≤ ƒTX ≤ 2050 MHz
TX_DIV_SEL = 2	TX DIV = 4	512.5 MHz ≤ ƒTX ≤ 1025 MHz
TX_DIV_SEL = 3	TX DIV = 8	256.25 MHz ≤ ƒTX ≤ 512.5 MHz
LO_DIV_SEL = 0	LO DIV = 1	2050 MHz ≤ ƒLO ≤ 4100 MHz
LO_DIV_SEL = 1	LO DIV = 2	1025 MHz ≤ ƒLO ≤ 2050 MHz
LO_DIV_SEL = 2	LO DIV = 4	512.5 MHz ≤ ƒLO ≤ 1025 MHz
LO_DIV_SEL = 3	LO DIV = 8	256.25 MHz ≤ ƒLO ≤ 512.5 MHz

2. PLL_DIV_SEL

Given f_VCO, select PLL_DIV_SEL so that the division ratio PLL DIV limits the input frequency to the prescaler , f_DMP, is limited to a maximum of 3000 MHz.

PLL DIV = min(1, 2, 4) such that f_DMP ≤ 3000 MHz

PLL DIV is related to PLL_DIV_SEL according to the following equation:

PLL_DIV = 2^PLL_DIV_SEL

This calculation can be restated as Equation 6.

Equation 6.

For both integer and fractional mode it is preferable to operate the f_PFD at the highest possible frequency determined by the required frequency step of the RFOUT or LO_OUT. In Integer mode, select the maximum f_PFD according to Equation 7.

Equation 7.

In Fractional mode, small RF stepsize can be obtained through the fractional divider. In this case, the highest f_PFD frequency should be selected according to the reference clock and system requirements.

3. RDIV, NINT, NFRAC, PRSC_SEL

The remaing PLL parameters are calculated according to the following equations:





The DMP division ratio (P/P+1) can be set to 4/5 or 8/9 through the PRSC_SEL bit. To allow proper fractional operation, set PRSC_SEL according to:

PRSC_SEL = 0, (P/P+1) = 4/5 for 20 ≤ NINT < 72 in integer mode or 23 ≤ NINT < 75 in fractional mode.

PRSC_SEL = 1, (P/P+1) = 8/9 for NINT ≥ 72 in integer mode or NINT ≥ 75 in fractional mode.

The PRSC_SEL limit at NINT < 75 applies to Fractional mode with third-order modulation. In Integer mode, the PRSC_SEL = 8/9 should be used with NINT as low as 72. The divider block accounts for either value of PRSC_SEL without requiring NINT or NFRAC to be adjusted. Then, calculate the maximum input frequency (f_N) to the digital divider. Use the lower of the possible prescaler divide settings, P = (4,8), as shown by Equation 8.

Equation 8.

Verify that the frequency into the digital divider, f_N, is less than or equal to 375 MHz. If f_N exceeds 375 MHz, choose a larger value for PLL_DIV_SEL and recalculate f_PFD, RDIV, NINT, NFRAC, and PRSC_SEL.

8.4.2 Setup Example for Integer Mode

Suppose the following operating characteristics fractional example are desired for Integer mode operation:

• f_REF = 61.44 MHz (reference input frequency)
• Step at RF = 2.56 MHz (RF channel spacing)
• f_RF = 1799.68 MHz (RF frequency)

The VCO range is 2050 MHz to 4100 MHz. Therefore:

• LO DIV = 2 (LO_DIV_SEL = 1)
• f_VCO = LO DIV × 1799.68 MHz = 3599.36 MHz

In order to keep the frequency of the prescaler below 3000 MHz:

• PLL_DIV = 2 (PLL_DIV_SEL = 1)

The desired stepsize at RF is 2.56 MHz, so:

• f_PFD = 2.56 MHz
• f_VCO, stepsize = PLL_DIV × f_PFD = 5.12 MHz

Using the reference frequency along with the required f_PFD gives:

• RDIV = 24
• NINT = 703

NINT ≥ 75; therefore, select the 8/9 prescaler.

This example shows that Integer mode operation gives sufficient resolution for the required stepsize.

8.4.3 Integer and Fractional Mode Selection

The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO) frequency is an integer multiple of f_PFD, then select integer mode otherwise select fractional mode. In Integer mode, the feedback divider ratio is an integer, and the fraction is zero. Thus, bits corresponding to the fractional control in integer mode are don’t care and fractional divider functionality is disabled.

In Fractional mode, the accuracy of the final frequency is set by 25-bit resolution. The RF stepsize is f_PFD/2²⁵ which is less than 1 Hz for f_PFD up to 33 MHz. The appropriate fractional control bits in the serial register must be programmed. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and ISOURCE_TRIM values according to the chosen frequency band.

8.4.4 Selecting the VCO and VCO Frequency Control

To achieve a broad frequency tuning range, the TRF3722 integrates multiple VCOs. Each VCO tank uses a bank of coarse tuning capacitor to bring VCO frequency within a few MHz of the desired value. For a given LO frequency an appropriate VCO and capacitor array must be selected. The device integrates logic that automatically selects an appropriate VCO and capacitor array, such that in closed loop V_(TUNE) is approximately equal to the open loop calibration reference voltage set by VCO_CAL_REF. An on-chip temperature sensor automatically adjusts this reference voltage so that proper lock can be maintained over the temperature range.

The calibration logic is driven by a CAL_CLK signal which is scaled version of the reference frequency according to CAL_CLK_SEL. For optimum accuracy It is recommended to limit the CAL_CLK frequency to 600 kHz.

When VCO_SEL_MODE is '0', the device automatically selects the VCO and the capacitor array. When VCO_SEL_MODE is '1', the VCO selected by VCO_SEL is used and the logic automatically selects the capacitor array. The VCO and capacitor array settings resulting from the calibration can be read from Register 0 - read back register.

Automatic calibration can be disabled by setting CAL_BYPASS to '1'. In this manual calibration mode, the VCO is selected through register bits VCO_SEL, while the capacitor array is selected through register bits VCO_TRIM. Calibration modes are summarized in Table 3.

Table 4. Serial interface Register Summary

8.5.1 Serial interface Register Definition

CAL_CLK_SEL[3..0]: Set the frequency divider value used to derive the VCO calibration clock from the reference frequency.

ICP[4..0]: Set the charge pump current.