ZHCSOO7A August 2021 – November 2021 TPSM8A28 , TPSM8A29
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY CURRENT | ||||||
| IQ_VIN | VIN operating nonswitching supply current | VEN = 2 V, VFB = 0.65 V, VIN = 12 V, no external bias on the VCC pin | 680 | 850 | μA | |
| ISD_VIN | VIN shutdown supply current | VEN = 0 V, VIN =12 V, no external bias on the VCC pin | 9.5 | 20 | μA | |
| IQ_VCC | VCC quiescent current | TJ = 25°C, VEN = 2 V, VFB = 0.65 V, VIN = 5 V, 5.0 V external bias on the VCC pin | 680 | 820 | μA | |
| ISD_VCC | VCC shutdown current | TJ = 25°C, VEN = 0 V, VIN = 0 V, 5.0 V external bias on the VCC pin | 75 | 85 | μA | |
| REFERENCE VOLTAGE | ||||||
| VINTREF | Internal REF voltage | TJ = 25°C | 600 | mV | ||
| Internal REF voltage tolerance | TJ = 0°C to 70°C | 597 | 603 | mV | ||
| Internal REF voltage tolerance | TJ = –40°C to 125°C | 594 | 606 | mV | ||
| IFB | FB input current | VFB = VINTREF | 50 | 100 | nA | |
| OUTPUT DISCHARGE | ||||||
| RDischg | Output discharge resistance | VIN = 12 V, VCC = internal LDO, Vsw = 0.5 V, power conversion disabled | 70 | Ω | ||
| SWITCHING FREQUENCY | ||||||
| fSW | VO switching frequency, FCCM operation | VIN = 12 V, VOUT = 1.2 V, RMODE = 0 Ω to AGND | 490 | 620 | 750 | kHz |
| VIN = 12 V, VOUT = 1.2 V, RMODE = 30.1 kΩ to AGND | 720 | 800 | 880 | |||
| VIN = 12 V, VOUT = 1.2 V, RMODE = 60.4 kΩ to AGND | 840 | 1000 | 1250 | |||
| tON(min) | Minimum on time | TJ = 25°C(1) | 70 | 85 | ns | |
| tOFF(min) | Minimum off time | TJ = 25°C, HS FET gate falling to rising(1) | 220 | ns | ||
| ENABLE | ||||||
| VENH | EN enable threshold voltage (rising) | 1.17 | 1.22 | 1.27 | V | |
| VENL | EN disable threshold voltage (falling) | 0.97 | 1.02 | 1.07 | V | |
| VENHYST | EN hysteresis voltage | 0.2 | V | |||
| VENLEAK | EN input leakage current | VEN = V | 0.5 | 5 | μA | |
| EN internal pulldown resistance | EN pin to AGND. EN floating disables the converter. | 6500 | k? | |||
| INTERNAL VCC LDO | ||||||
| VCC | Internal LDO output voltage | VIN = 12 V, ILOAD = 2 mA | 4.32 | 4.5 | 4.68 | V |
| VCCUVLO | VCC undervoltage-lockout (UVLO) threshold voltage | VCC rising | 2.80 | 2.87 | 2.94 | V |
| VCC falling | 2.62 | 2.7 | 2.77 | V | ||
| VCCUVLO | VCC undervoltage-lockout (UVLO) threshold voltage | VCC hysteresis | 0.17 | V | ||
| VCCDO | LDO low-droop dropout voltage | VIN = 3.0 V, IVCC_LOAD = 2 mA, TJ = 25°C | 62 | 75 | mV | |
| LDO overcurrent limit | All VINs, all temperature | 105 | 158 | mA | ||
| STARTUP | ||||||
| tSS | Soft-start time | VO rising from 0 V to 95% of final setpoint, CSS/REFIN = open | 1 | 1.5 | ms | |
| SS/REFIN sourcing current | VSS/REFIN = 0 V | 36 | μA | |||
| SS/REFIN sinking current | VSS/REFIN = 1 V | 12 | μA | |||
| EN to first switching delay, internal LDO | The delay from EN goes high to the first SW rising edge with internal LDO configuration. CVCC = 2.2 μF. CSS/REFIN = 220 nF | 0.93 | 2 | ms | ||
| EN to first switching delay, external VCC bias | The delay from EN goes high to the first SW rising edge with external VCC bias configuration. VCC bias must reach regulation before EN ramp up. CSS/REFIN = 220 nF. | 550 | 900 | μs | ||
| PGOOD COMPARATOR | ||||||
| VPGTH | PGOOD threshold | FB rising, PGOOD low to high | 89% | 92.5% | 95% | |
| FB rising, PGOOD high to low | 113% | 116% | 119% | |||
| FB falling, PGOOD high to low | 77% | 80% | 83% | |||
| VPGTH | OOB (out-of-bounds) threshold | FB rising, PGOOD stays high | 103% | 105.5% | 108% | |
| IPG | PGOOD sink current | VPGOOD = 0.4 V, VIN = 12 V, VCC = Internal LDO | 25 | mA | ||
| IPG | PGOOD low-level output voltage | IPGOOD = 5.5 mA, VIN = 12 V, VCC = internal LDO | 400 | mV | ||
| tPG_delay | PGOOD delay time | Delay for PGOOD from low to high | 1.0 | 1.4 | ms | |
| Delay for PGOOD from high to low | 0.5 | 5 | μs | |||
| IPG_lkg | PGOOD leakage current when pulled high | TJ = 25°C, VPGOOD = 3.3 V, VFB = VINTREF | 5 | μA | ||
| PGOOD clamp low-level output voltage | VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 100-kΩ resistor | 710 | 850 | mV | ||
| VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 10-kΩ resistor | 850 | 1000 | mV | |||
| Minimum VCC for valid PGOOD output | 1.5 | V | ||||
| OVERCURRENT PROTECTION | ||||||
| RTRIP | TRIP pin resistance range | TPSM8A28 | 4.02 | 14.7 | kΩ | |
| RTRIP | TRIP pin resistance range | TPSM8A29 | 0 | 14.7 | kΩ | |
| IOCL | Current limit threshold, TPSM8A29 only | Valley current on LS FET, 0 kΩ ≤ RTRIP ≤ 3.3 kΩ TPSM8A29 only | 14.8 | 18.4 | 21.7 | A |
| IOCL | Current limit threshold | Valley current on LS FET, RTRIP = 4.02 kΩ | 12.0 | 14.2 | 16.3 | A |
| IOCL | Current limit threshold | Valley current on LS FET, RTRIP = 4.99 kΩ | 9.9 | 12.0 | 14.1 | A |
| IOCL | Current limit threshold | Valley current on LS FET, RTRIP = 10 kΩ | 3.9 | 6.0 | 8.1 | A |
| KOCL | KOCL for RTRIP equation | 60000 | A Ω | |||
| INOCL | Negative current limit threshold | All VINs | –12 | –10 | –8 | A |
| IZC | Zero-cross detection current threshold, open loop | VIN = 12 V, VCC = Internal LDO | 400 | mA | ||
| UVLO | ||||||
| VINUVLO | VIN UVLO threshold voltage | Rising | 2.1 | 2.4 | 2.7 | V |
| Falling | 1.55 | 1.85 | 2.15 | V | ||
| VOVP | Overvoltage-protection (OVP) threshold voltage | 113% | 116% | 119% | ||
| THERMAL SHUTDOWN | ||||||
| TSDN | Thermal shutdown threshold(1) | Temperature rising | 165 | °C | ||
| Thermal shutdown hysteresis(1) | 30 | °C | ||||