ZHCSPT6D July 2023 – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15
PRODUCTION DATA
Table 8-1 lists the Device registers. All register addresses not listed in Table 8-1 must be considered as reserved locations and the register contents must not be modified.
| Address | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | VSET | Output Voltage Setpoint | Go |
| 1h | CONTROL1 | Control 1 | Go |
| 2h | CONTROL2 | Control 2 | Go |
| 3h | CONTROL3 | Control 3 | Go |
| 4h | STATUS | Status | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| - n | Value after reset or the default value | |
VSET is shown in Figure 8-1 and described in Table 8-3.
Return to the Summary Table.
This register controls the output voltage setpoint
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VSET | |||||||
| R/W-X | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | VSET | R/W | X | Output voltage setpoint (see also the range-setting bits in the CONTROL2 register). Range 1: Output voltage setpoint = 0.4 V + VSET[7:0] × 1.25 mV Range 2: Output voltage setpoint = 0.4 V + VSET[7:0] × 2.5 mV Range 3: Output voltage setpoint = 0.4 V + VSET[7:0] × 5 mV Range 4: Output voltage setpoint = 0.8 V + VSET[7:0] × 10 mV The state of the VSETx pins during power up determines the reset value. (See Table 7-2). |
CONTROL1 is shown in Figure 8-2 and described in Table 8-4.
Return to the Summary Table.
This register controls various device configuration options
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESET | SSCEN | SWEN | FPWMEN | DISCHEN | HICCUPEN | VRAMP | |
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | R/W-10b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESET | R/W | 0b | Reset device. 0b = No effect 1b = Resets all registers to the default values. The device then performs another initialization. |
| 6 | SSCEN | R/W | 0b | Spread spectrum clocking enable. 0b = SSC operation disabled 1b = SSC operation enabled |
| 5 | SWEN | R/W | 1b | Software enable. 0b = Switching disabled (register values retained) 1b = Switching enabled (without the enable delay td(EN)1) |
| 4 | FPWMEN | R/W | 0b | Forced-PWM enable. 0b = Power-save operation enabled 1b = Forced-PWM operation enabled This bit is logically ORed with the MODE/SYNC pin: If a high level or a synchronization clock is applied to the the MODE/SYNC pin, the device operates in Forced-PWM, regardless of the state of this bit. |
| 3 | DISCHEN | R/W | 1b | Output discharge enable. 0b = Output discharge disabled. 1b = Output discharge enabled. |
| 2 | HICCUPEN | R/W | 0b | Hiccup operation enable. 0b = Hiccup operation disabled 1b = Hiccup operation enabled. Do not enable Hiccup operation during stacked operation |
| 1-0 | VRAMP | R/W | 10b | Output voltage ramp speed when changing from one output voltage setting to another. 00b = 10 mV/μs 01b = 5 mV/μs 10b = 1.25 mV/μs 11b = 0.5 mV/μs |
CONTROL2 is shown in Figure 8-3 and described in Table 8-5.
Return to the Summary Table.
This register controls various device configuration options
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VRANGE | SSTIME | |||||
| R-0000b | R/W-X | R/W-01b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R | 0000b | Reserved for future use. To make sure compatibility with future device variants, program these bits to 0. |
| 3-2 | VRANGE | R/W | X | Output voltage range. 00b = 0.4 V to 0.71875 V in 1.25-mV steps 01b = 0.4 V to 1.0375 V in 2.5-mV steps 10b = 0.4 V to 1.675 V in 5-mV steps 11b = 0.8 V to 3.35 V in 10-mV steps. The state of the VSETx pins during power up determines the reset value. See Table 7-2. |
| 1-0 | SSTIME | R/W | 01b | Soft-start ramp time. 00b = 0.5 ms 01b = 1 ms 10b = 2 ms 11b = 4 ms |
CONTROL3 is shown in Figure 8-4 and described in Table 8-6.
Return to the Summary Table.
This register controls various device configuration options
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SINGLE | PGBLNKDVS | |||||
| R-000000b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R | 000000b | Reserved for future use. To make sure compatibility with future device variants, program these bits to 0. |
| 1 | SINGLE | R/W | 0b | Single operation. This bit controls the internal EN pulldown and SYNC_OUT functions. 0b = EN pin pulldown and SYNC_OUT enabled.
|
| 0 | PGBLNKDVS | R/W | 0b | Power-good blanking during DVS. 0b = PG pin reflects the output of the window comparator 1b = PG pin is high impedance during DVS |
STATUS is shown in Figure 8-5 and described in Table 8-7.
Return to the Summary Table.
This register returns the device status flags
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | HICCUP | ILIM | TWARN | TSHUT | PBUV | PBOV | |
| R-00b | R-0b | R-0b | R-0b | R-0b | R-1b | R-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 00b | Reserved for future use. To make sure compatibility with future device variants, ignore these bits. |
| 5 | HICCUP | R | 0b | Hiccup. This bit reports whether a hiccup event occurred since the last time the STATUS register was read. 0b = No hiccup event occurred 1b = A hiccup event occurred |
| 4 | ILIM | R | 0b | Current limit. This bit reports whether a current limit event occurred since the last time the STATUS register was read. 0b = No current limit event occurred 1b = A current limit event occurred |
| 3 | TWARN | R | 0b | Thermal warning. This bit reports whether a thermal warning event occurred since the last time the STATUS register was read. 0b = No thermal warning event occurred 1b = A thermal warning event occurred |
| 2 | TSHUT | R | 0b | Thermal shutdown. This bit reports whether a thermal shutdown event occurred since the last time the STATUS register was read. 0b = No thermal shutdown event occurred 1b = A thermal shutdown event occurred |
| 1 | PBUV | R | 1b | Power-bad undervoltage. This bit reports whether a power-bad event (output voltage too low) occurred since the last time the STATUS register was read. 0b = No power-bad undervoltage event occurred 1b = A power-bad undervoltage event occurred |
| 0 | PBOV | R | 0b | Power-bad overvoltage. This bit reports whether a power-bad event (output voltage too high) occurred since the last time the STATUS register was read. 0b = No power-bad overvoltage event occurred 1b = A power-bad overvoltage event occurred |