ZHCSK69F August 2019 – November 2021 TPSM82821 , TPSM82821A , TPSM82822 , TPSM82822A , TPSM82823 , TPSM82823A
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The device has a power good output. The PG pin goes high impedance once the FB pin voltage is above 96% and less than 105% of the nominal voltage, and is driven low once the voltage falls below typically 92% or higher than 110% of the nominal voltage. Table 8-1 shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pullup resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails by connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND.
| DEVICE STATE | PG LOGIC STATUS | ||
|---|---|---|---|
| HIGH IMPEDANCE | LOW | ||
| Enabled (EN = High) | 0.576 V ≤ VFB ≤ 0.63 V |
√ | |
| VFB < 0.552 V or VFB > 0.66 V | √ | ||
| Shutdown (EN = Low) | √ | ||
| UVLO |
0.7 V ≤ VIN < VUVLO | √ | |
| Thermal Shutdown |
TJ > TJSD | √ | |
| Power Supply Removal |
VIN < 0.7 V | √ | |
The PG pin has a 20-μs deglitch time on the falling edge and a 100-μs delay before PG goes high. See Figure 8-1.