ZHCSKB4C September 2019 – December 2024 TPSM82810 , TPSM82813
PRODMIX
The device has a power good output with window comparator. The PG pin goes high impedance after the FB pin voltage is above 95% and less than 107% of the nominal voltage, and is driven low after the voltage falls below typically 90% or higher than 110% of the nominal voltage. Table 8-2 shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 2mA. The power good output requires a pullup resistor connected to any voltage rail less than VIN. The PG signal can be used for sequencing of multiple rails by connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND.
| DEVICE STATE | PG LOGIC STATUS | ||
|---|---|---|---|
| HIGH IMPEDANCE | LOW | ||
| Enabled (EN = High) | 0.57V ≤ VFB ≤ 0.642V |
√ | |
| VFB < 0.54V or VFB > 0.66V | √ | ||
| Shutdown (EN = Low) | √ | ||
| UVLO |
2V ≤ VIN < VUVLO | √ | |
| Thermal Shutdown |
TJ > TJSD | √ | |
| Power Supply Removal |
VIN < 2V | √ | |
The PG pin has a 40μs deglitch time on the falling edge.