Figure 8-4 shows the basic setup required for two-wire mode operation, which requires the EN signal and VSSP ground signal. EN can be driven up to 48 V. No current limiting resistor is required on EN because the TPSI3052-Q1 limits the input current based on the values set by the R_PXFR resistor (see Table 8-2). In this example, the TPSI3052-Q1 is being used to drive back-to-back MOSFETs in a common-source configuration. C_VDDP provides the required decoupling capacitance for the VDDP supply rail of the device. C_DIV1 and C_DIV2 provide the required decoupling capacitance of the VDDH and VDDM supply rails that provide the peak current to drive the external MOSFETs.

Figure 8-5 shows the typical operation in two-wire mode configured for standard enable. The application drives EN to a logic high and the TPSI3052-Q1 begins its power-up sequence. During power up, the current provided by the EN pin, I_EN, begins to charge up the external capacitance, C_VDDP, and the voltage on VDDP begins to rise until it reaches V_{VDDP_H}. After VDDP reaches its peak, V_{VDDP_H}, the TPSI3052-Q1 transfers stored energy on C_VDDP to the secondary side for a fixed time (3.3-μs typical) which begins to charge up the VDDH (and VDDM) secondary side rails thereby discharging the voltage on VDDP. In steady state, this results in an average voltage on VDDP, V_{VDDP_AVG}. This cycle repeats until the VDDH (and VDDM) secondary side rails are fully charged. The time required to fully charge VDDH depends on several factors including the values of C_VDDP, C_DIV1, C_DIV2, R_PXFR, and the overall power transfer efficiency. After VDDH is fully charged, VDRV is asserted high and remains high while the EN pin remains at a logic high. When the application drives the EN pin to a logic low, the charge on VDDP begins to discharge. Prior to VDDP reaching its UVLO falling threshold, TPSI3052-Q1 signals information from the primary side to the secondary side to de-assert VDRV and drive it low. Because power is no longer being transferred, all rails begin to fully discharge.

Figure 8-4 Two-Wire Mode Simplified Schematic

Figure 8-5 Two-Wire Mode with Standard Enable (TPSI3052-Q1 Only)

In two-wire mode, power is supplied directly by the EN pin. When EN is asserted high, the TPSI3052-Q1 transfers power to the secondary side for a fixed time (3.3-μs nominal) while the time period varies. The period varies due to the hysteretic control of the power transfer that ensures the average current supplied through the EN pin is maintained. The amount of average current, and hence the amount of power transferred, is programmable by selecting one of seven appropriate resistor values, R_PXFR, from the PXFR to VSSP pins. Higher settings of R_PXFR increase I_EN which increases the average power consumed from the EN pin and increases the amount of power transferred to the secondary side VDDH supply. Similarly, lower settings of R_PXFR decrease I_EN, which decreases the average power consumed from the EN pin and decreases the amount of power transferred to the secondary side.

Table 8-2 summarizes the two-wire mode power selection.