ZHCSOF4A February 2022 – September 2022 TPS7H5005-SEP , TPS7H5006-SEP , TPS7H5007-SEP , TPS7H5008-SEP
PRODUCTION DATA
The leading edge blank time was initially chosen to be roughly 50 ns. This value was the initial approximation based on any ringing or transient spikes that were expected to be seen on the sensed current waveform at the CS_ILIM pin. Using Equation 9, the value of RLEB was calculated from this desired value.
The value of RLEB selected was 49.9 kΩ. Note that the ringing and transient spikes on the sensed current waveform will depend heavily on component placement and parastics in the PCB layout. The leading edge blank time should also account for any propagation delay that is inherent to the gate driver being used in the application. As such, the value of RLEB may need to be optimized as the design is tested in accommodate for these factors. Recall that the leading edge blank time is also correlated to the minimum on-time of the device, and extending this value significantly may become a limiting factor for the maximum switching frequency that can be achieved in the design.