ZHCSOF4A February 2022 – September 2022 TPS7H5005-SEP , TPS7H5006-SEP , TPS7H5007-SEP , TPS7H5008-SEP
PRODUCTION DATA
| PIN | I/O | DESCRIPTION | ||||
|---|---|---|---|---|---|---|
| NAME | TPS7H5005-SEP | TPS7H5006-SEP | TPS7H5007-SEP | TPS7H5008-SEP | ||
| RT | 1 | 1 | 1 | 1 | I/O | In internal oscillation mode, the RT pin must be populated with a resistor to AVSS. When the RT pin is floating, a 200-kHz to 4-MHz external clock is required at the SYNC pin. The frequency of the external clock must be twice the desired switching frequency. |
| PS | 2 | 2 | — | — | I/O | Primary off to synchronous rectifier on dead-time set. Programmable through an external resistor to AVSS. |
| SP | 3 | 3 | — | — | I/O | Synchronous rectifier off to primary on dead-time set. Programmable through an external resistor to AVSS. |
| LEB | 4 | 4 | — | 4 | I/O | Leading edge blank time set. Programmable through an external resistor to AVSS. |
| HICC | 5 | 5 | 5 | 5 | I/O | Cycle-by-cycle current limit time delay and hiccup time setting. Delay time and hiccup time determined by capacitor from HICC to AVSS. Connecting this pin to AVSS disables hiccup mode. |
| SYNC | 6 | 6 | 6 | 6 | I/O | When the RT pin is floating, SYNC is configured as an input for a 200-kHz to 4-MHz external clock. In this case, the external clock input gets inverted and the system clock will run at half the frequency of the external clock input. When the RT pin is populated with a resistor to AVSS, SYNC outputs a 200-kHz to 4-MHz clock signal at twice the device switching frequency in phase with the switching of the device. |
| DCL | 7 | 7 | 7 | 7 | I/O | Duty cycle limit configurability. For TPS7H5005-SEP, connect to AVSS for 50% duty cycle limit, floating for 75%, and VLDO for 100%. For TPS7H5006-SEP and TPS7H5007-SEP, the DCL pin can be left floating or connected to VLDO to set the maximum duty cycle to 75% or 100%, respectively. For TPS7H5008-SEP, this pin must be connected to AVSS in order to obtain the 50% maximum duty cycle. |
| EN | 8 | 8 | 8 | 8 | I | Connecting the EN pin to the VLDO pin or external source greater than 0.6 V enables the device. In addition, input undervoltage lockout (UVLO) can be adjusted with two resistors. |
| VIN | 9 | 9 | 9 | 9 | I | Input supply to the device. Input voltage range is from 4 V to 14 V. |
| OUTA | 10 | 10 | 10 | 10 | O | Primary switching output A. |
| OUTB | 11 | — | — | 11 | O | Primary switching output B. Active only when DCL = AVSS. |
| SRB | 14 | — | — | — | O | Synchronous rectifier output B. Active only when DCL = AVSS. |
| SRA | 15 | 15 | 15 | — | O | Synchronous rectifier output A. |
| AVSS | 16 | 16 | 16 | 16 | — | Ground of the device. |
| VLDO | 17 | 17 | 17 | 17 | O | Output of internal regulator. Requires at least 1-μF external capacitor to AVSS. |
| CS_ILIM | 18 | 18 | 18 | 18 | I/O | Current sense for PWM control and cycle-by-cycle overcurrent protection. An input voltage over 1.05 V on CS_ILIM will trigger an overcurrent in the PWM controller. The sensed waveform on CS_ILIM contains a 150-mV offset when compared to the COMP/2 voltage at the input of the PWM comparator. |
| FAULT | 19 | 19 | 19 | 19 | I | Fault protection pin. When the rising threshold of the FAULT pin is exceeded, the outputs will stop switching. After the external voltage drops below the falling threshold, the device will restart after a set delay. Connect this pin to AVSS to disable FAULT. |
| REFCAP | 20 | 20 | 20 | 20 | O | 1.2-V internal reference. Requires a 470-nF external capacitor to AVSS. |
| RSC | 21 | 21 | 21 | 21 | I/O | A resistor from RSC to AVSS sets the desired slope compensation. |
| SS | 22 | 22 | 22 | 22 | I/O | Soft start. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing. |
| VSENSE | 23 | 23 | 23 | 23 | I | Inverting input of the error amplifier. |
| COMP | 24 | 24 | 24 | 24 | I/O | Error amplifier output. Connect frequency compensation to this pin. |
| NC | 12, 13 | 11, 12, 13, 14 | 2, 3, 4, 11, 12, 13, 14 | 2, 3, 12, 13, 14, 15 | — | No connect. Can be connected to AVSS to avoid floating metal if desired. |