ZHCSOH8F July 2021 – August 2024 TPS7H5001-SP , TPS7H5002-SP , TPS7H5003-SP , TPS7H5004-SP
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Device Comparison Table
- 5 Device Options
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics: All Devices
- 7.6 Electrical Characteristics: TPS7H5001-SP
- 7.7 Electrical Characteristics: TPS7H5002-SP
- 7.8 Electrical Characteristics: TPS7H5003-SP
- 7.9 Electrical Characteristics: TPS7H5004-SP
- 7.10 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VIN and VLDO
- 8.3.2 Start-Up
- 8.3.3 Enable and Undervoltage Lockout (UVLO)
- 8.3.4 Voltage Reference
- 8.3.5 Error Amplifier
- 8.3.6 Output Voltage Programming
- 8.3.7 Soft Start (SS)
- 8.3.8 Switching Frequency and External Synchronization
- 8.3.9 Primary Switching Outputs (OUTA/OUTB)
- 8.3.10 Synchronous Rectifier Outputs (SRA and SRB)
- 8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
- 8.3.12 Pulse Skipping
- 8.3.13 Duty Cycle Programmability
- 8.3.14 Current Sense and PWM Generation (CS_ILIM)
- 8.3.15 Hiccup Mode Operation (HICC)
- 8.3.16 External Fault Protection (FAULT)
- 8.3.17 Slope Compensation (RSC)
- 8.3.18 Frequency Compensation
- 8.3.19 Thermal Shutdown
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Switching Frequency
- 9.2.2.2 Output Voltage Programming Resistors
- 9.2.2.3 Dead Time
- 9.2.2.4 Leading Edge Blank Time
- 9.2.2.5 Soft-Start Capacitor
- 9.2.2.6 Transformer
- 9.2.2.7 Main Switching FETs
- 9.2.2.8 Synchronous Rectificier FETs
- 9.2.2.9 RCD Clamp
- 9.2.2.10 Output Inductor
- 9.2.2.11 Output Capacitance and Filter
- 9.2.2.12 Sense Resistor
- 9.2.2.13 Hiccup Capacitor
- 9.2.2.14 Frequency Compensation Components
- 9.2.2.15 Slope Compensation Resistor
- 9.2.3 Application Curves
- 9.3 Power Supply Recommendations
- 9.4 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- HFT|22
- KGD|0
- PW|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
8.3.8.3 Primary-Secondary Mode
Two TPS7H500x-SP controllers can be operated in a primary-secondary mode by utilizing the SYNC pin. As mentioned in the Internal Oscillator section, when RT is selected to provide the desired switching frequency, SYNC outputs a clock signal at twice the switching frequency. As such, the clock input generated by the primary device be used as the clock input at SYNC for the secondary controller, which would operate in external synchronization mode. This means that the RT pin of the primary device should be populated while the corresponding pin of the secondary device would be left floating.
The primary-secondary mode would be useful in a couple of scenarios. The first is for two independent converters that need to be synchronized to the same switching frequency. In this instance, the converters can be two converters can have different operating conditions or topologies. Besides the shared SYNC signal, there are no connections between the two converters.
Figure 8-10 Primary-Secondary Mode
Configuration for Two Independent ConvertersIn a second scenario, two controllers can be used to design a single interleaved converter with phases in parallel. In this design, the VSENSE, COMP, SS, and HICC pins would need to be connected in addition to the shared SYNC connection.
Figure 8-11 Primary-Secondary Mode
Configuration for Parallel OperationWhen using two controllers in primary-secondary mode, it is important to note that secondary controller will invert the clock signal that it receives from the primary controller. As such, there will be phase shift between the switching outputs of the primary and secondary controllers. This phase shift from an output (i.e. OUTA) on the primary controller to the corresponding output on the secondary controller will be 90° or 270°, depending on when the secondary device synchronizes to its clock input. Note that in Figure 8-12, the waveforms for OUTB are only applicable for TPS7H5001-SP and TPS7H5004-SP.
Figure 8-12 Switching Waveforms for
Primary-Secondary ModeThe three operational modes for the controller are summarized in Table 8-1.
| MODE | RT | SYNC | SWITCHING FREQUENCY |
|---|---|---|---|
| Internal oscillator | Populated with resistor to AVSS. | Configured as output. Generates in-phase clock at twice the switching frequency. | Configurable from 100 kHz to 2 MHz depending on RT value. |
| External synchronization | Floating. | Configured as input. Accepts 200-kHz to 4-MHz external clock that is inverted internally. | Synchronized to SYNC input clock at 1/2 of the clock frequency. Switching is out-of-phase with external clock. |
| Primary-secondary | Populated with resistor to AVSS on primary device. Floating on secondary device. | Configured as output on primary device. Configured as input on secondary device. The SYNC pins of primary and secondary devices are connected. | Configurable from 100 kHz to 2 MHz depending on RT value of primary device. Secondary device switching is either 90° or 270° out-of-phase with primary device. |