ZHCSL64D april 2019 – may 2023 TPS7H4001-SP
PRODMIX
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Options Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics - All Devices
- 7.6 Electrical Characteristics: CDFP and KGD Options
- 7.7 Electrical Characteristics: HTSSOP (SHP) Option
- 7.8 Electrical Characteristics: HTSSOP (QMLP) Option
- 7.9 Quality Conformance Inspection
- 7.10 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VIN and Power VIN Pins (VIN and PVIN)
- 8.3.2 Voltage Reference
- 8.3.3 Adjusting the Output Voltage
- 8.3.4 Safe Start-Up Into Prebiased Outputs
- 8.3.5 Error Amplifier
- 8.3.6 Enable and Adjust UVLO
- 8.3.7 Adjustable Switching Frequency and Synchronization (SYNC)
- 8.3.8 Soft-Start (SS/TR)
- 8.3.9 Power Good (PWRGD)
- 8.3.10 Sequencing
- 8.3.11 Output Overvoltage Protection (OVP)
- 8.3.12 Overcurrent Protection
- 8.3.13 Thermal Shutdown
- 8.3.14 Turn-On Behavior
- 8.3.15 Slope Compensation
- 8.3.16 Small Signal Model for Frequency Compensation
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Operating Frequency
- 9.2.2.2 Output Inductor Selection
- 9.2.2.3 Output Capacitor Selection
- 9.2.2.4 Input Capacitor Selection
- 9.2.2.5 Soft-Start Capacitor Selection
- 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
- 9.2.2.7 Output Voltage Feedback Resistor Selection
- 9.2.2.8 Compensation Component Selection
- 9.2.3 Parallel Operation
- 9.2.4 Application Curve
- 9.3 Power Supply Recommendations
- 9.4 Layout
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- DDW|44
- KGD|0
- HKY|34
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DDW|44
訂購信息
9.2.2.4 Input Capacitor Selection
The TPS7H4001-SP requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 μF of effective capacitance on the PVIN input voltage pins, and 4.7 μF on the VIN input voltage pin. In some applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS7H4001-SP. The input ripple current can be calculated using Equation 30.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. For this example, six 22-μF and two 470-μF 25-V capacitors in parallel have been selected as the VIN and PVIN inputs are tied together so the TPS7H4001-SP may operate from a single supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 31. Using the design example values, IOMAX = 18 A, CIN = 1.072 mF, fSW = 500 kHz, yields an input voltage ripple of 8.4 mV and a RMS input ripple current of 7.2 A.
