ZHCSOS3F August 2021 – March 2024 TPS7H2211-SEP , TPS7H2211-SP
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
For best performance, make all traces as short as possible. Place the input and output capacitors close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Use wide traces for VIN, VOUT, and GND to help minimize the parasitic electrical effects. Pay particular attention to minimizing the length of the CSS capacitor connection between VOUT and SS in order to minimize stray inductance.
Use thermal vias for the thermal pad to ensure the device remains at allowable temperatures, especially during fault conditions (such as a short at VOUT). As the thermal pad is internally connected to GND, TI recommends the vias be connected to a large GND plane on the printed circuit board.