ZHCSBU8D October 2013 – April 2018
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE AND CURRENT (VIN) | |||||||
| VI | Input voltage | Fixed 3.3-V output, IO = 0 mA to 450 mA | 4 | 40 | V | ||
| Fixed 5-V output, IO = 0 mA to 450 mA | 5.5 | 40 | |||||
| Adjustable output, VO ≤ 3.5 V, IO = 0 mA to 450 mA | 4 | 40 | |||||
| Adjustable output, VO ≥ 3.5 V, IO = 0 mA to 450 mA | VO + 0.5 | 40 | |||||
| IQ | Quiescent current | VI = 5.5 V to 40 V (fixed 5 V), 4 V to 40 V (fixed 3.3 V),
EN = ON, IO = 0.2 mA |
15 | 25 | µA | ||
| VI = 4 V to 40 V (adjustable version, VO = 1.5 V),
EN = ON, IO = 0.2 mA |
15 | 25 | |||||
| VI = 18.5 V to 40 V (adjustable version, VO = 18 V),
EN = ON, IO = 0.2 mA |
25 | 35 | |||||
| ISleep | Input sleep current | NO load current and EN = OFF | 4 | µA | |||
| IEN | EN pin current | EN = 40 V | 1 | µA | |||
| Vbg | Band gap | Reference voltage for ADJ | –2% | 1.233 | 2% | V | |
| VINUVLO | Undervoltage detection | Ramp VI down until output is turned OFF | 2.6 | V | |||
| UVLOHys | Undervoltage detection hysteresis | 1 | V | ||||
| ENABLE INPUT (EN) | |||||||
| VIL | Logic input low level | 0 | 0.4 | V | |||
| VIH | Logic input high level | 1.7 | V | ||||
| REGULATED OUTPUT (VOUT) | |||||||
| VO | Regulated output(1) | VI = VO + 0.5 V to 40 V and VI ≥ 4 V, IO = 0 mA to 450 mA | –2% | 2% | |||
| ΔVO(ΔVI) | Line regulation | VI = VO + 1 V to 40 V and VI ≥ 4 V, IO = 100 mA, ?VO | 10 | mV | |||
| ΔVO(ΔIL) | Load regulation | IO = 1 mA to 450 mA, ?VO | 10 | mV | |||
| Vdropout | Dropout voltage | VI – VO, IO = 400 mA | 240 | 450 | mV | ||
| VI – VO, IO = 200 mA | 160 | 300 | |||||
| IO | Output current | VO in regulation | 0 | 450 | mA | ||
| Ilreg-CL | Output current-limit | VO short to ground | 140 | 360 | mA | ||
| VO = VO typical × 0.9 | 470 | 850 | |||||
| PSRR | Power-supply ripple rejection(2) | IL = 100 mA, CO = 22 µF | Freq = 100 Hz | 60 | dB | ||
| Freq = 100 kHz | 40 | ||||||
| RESET | |||||||
| VOL | Reset pulled low | IOL = 0.5 mA | 0.4 | V | |||
| IOH | Reset pulled VOUT through
10-kΩ resistor |
Leakage current | 1 | µA | |||
| VTH-(POR) | Power-on-reset threshold | VO power-up set tolerance | 89.6 | 91.6 | 93.6 | % of VOUT | |
| Vhys | Hysteresis | VO power-down set tolerance | 2 | % of VOUT | |||
| RESET DELAY | |||||||
| IChg | Delay capacitor charging current | Rdelay = 0 V | 6 | 9.5 | 14 | µA | |
| Vth | Threshold to release RESET high | 1 | V | ||||
| OPERATING TEMPERATURE RANGE | |||||||
| TJ | Junction temperature | –40 | 150 | °C | |||
| Tsd | Junction shutdown temperature | 175 | °C | ||||
| Thys | Hysteresis of thermal shutdown | 24 | °C | ||||