SBVS441 December 2022 TPS7B4255
PRODUCTION DATA
To improve AC performance (such as PSRR, output noise, and transient response), design the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of the device.
Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure stability. Every capacitor must be placed as close as possible to the device and on the same side of the printed circuit board (PCB) as the regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. Using vias and long traces is strongly discouraged because of the negative impact on system performance. Vias and long traces can also cause instability.
If possible, and to make sure that the maximum performance is as denoted in this product data sheet, use the same layout pattern used for the TPS7B4255 evaluation board, available at www.ti.com.