ZHCSF74A March 2016 – July 2016 TPS7A87
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
10 Layout
10.1 Layout Guidelines
General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance.
10.1.1 Board Layout
To maximize the performance of the device, following the layout example illustrated in Figure 65 is recommended. This layout isolates the analog ground (AGND) from the noisy power ground. Components that must be connected to the quiet analog ground are the noise-reduction capacitors (CNR/SSx) and the lower feedback resistors (R2x). These components must have a separate connection back to the thermal pad of the device. To minimize crosstalk between the two outputs, the output capacitor grounds are positioned on opposite sides of the layout and only connect back to the device at opposite sides of the thermal pad. Connecting the GND pins directly to the thermal pad and not to any external plane is recommended.
To maximize the output voltage accuracy, the connection from each output voltage back to the top output divider resistors (R1x) must be made as close as possible to the load. This method of connecting the feedback trace eliminates the voltage drop from the device output to the load.
To improve thermal performance, a 3 × 3 thermal via array must connect the thermal pad to internal ground planes. A larger area for the internal ground planes improves the thermal performance and lowers the operating temperature of the device.
10.2 Layout Example
Figure 65. TPS7A87 Example Layout