8.1.1.1 Adjustable Operation

The TPS7A85A can be used with the internal ANY-OUT network or by using external resistors. Using the ANY-OUT network allows the TPS7A85A to be programmed from 0.8 V to 3.95 V. For output voltage range greater than 3.95 V and up to 5.1 V, external resistors must be used. This configuration is referred to as the adjustable configuration of the TPS7A85A throughout the data sheet. The output voltage is set by two resistors, as shown in Figure 50. 0.75% accuracy can be achieved with an external BIAS for V_IN lower than 2.2 V.

Figure 50. Adjustable Operation

R₁ and R₂ can be calculated for any output voltage range using . This resistive network must provide a current equal to or greater than 5 μA for dc accuracy. TI recommends using an R₁ approximately 12 kΩ to optimize the noise and PSRR.

Equation 1.

Table 4 lists the resistor combinations required to achieve several common rails using standard 1%-tolerance resistors.

8.1.1.2 ANY-OUT Programmable Output Voltage

The TPS7A85A can use external resistors or the internally-matched ANY-OUT feedback resistor network to set output voltage. The ANY-OUT resistors are accessible through pin 2 and pins 5 to 11 and program the regulated output voltage. Each pin can be connected to ground (active), left open (floating), or connected to SNS. ANY-OUT programming is set by as the sum of the internal reference voltage (V_NR/SS = 0.8 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV (pin 6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 5 lists the voltage values associated with each active pin setting for reference. By leaving all program pins open or floating, the output is programmed to the minimum possible output voltage equal to V_FB.

Equation 2.

Table 6 lists target output voltages and corresponding pin settings when the ANY-OUT pins are only tied to ground or left floating. The voltage setting pins have a binary weight, so the output voltage can be programmed to any value from 0.8 V to 3.95 V in 50-mV steps when tying these pins to ground. There are several alternative ways to set the output voltage. The program pins can be driven using external general-purpose input or output pins (GPIOs), manually connected using 0-Ω resistors (or left open), or hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. As with the adjustable operation, the output voltage is set according to except that R₁ and R₂ are internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal feedback network by decreasing the value of R₁. See Increasing ANY-OUT Resolution for LILO Conditions for additional information.

Equation 3.

8.1.1.3 ANY-OUT Operation

Considering the use of the ANY-OUT internal network where the unit resistance of 1R, as shown in () is equal to 6.05 kΩ, the output voltage is set by grounding the appropriate control pins as shown in Figure 51. When grounded, all control pins add a specific voltage on top of the internal reference voltage (V_NR/SS = 0.8 V). The output voltage can be calculated by and . Figure 51 and Figure 52 show a 0.9-V output voltage (respectively) that show an example of the circuit usage with and without bias voltage.

Figure 51. ANY-OUT Configuration Circuit
(3.3-V Output, No External Bias)

Equation 4.

Figure 52. ANY-OUT Configuration Circuit
(0.9-V Output with Bias)

Equation 5.

8.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions

As with the adjustable operation, the output voltage is set according to Equation 5. However, R₁ and R₂ are internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal feedback network by decreasing the value of R₁. One of the more useful pin combinations is to tie the 800mV pin to SNS, which reduces the resolution by 50% to 25 mV but limits the range. The new ANY-OUT ranges are 0.8 V to 1.175 V and 1.6 V to 1.975 V. Table 7 lists the new additive output voltage levels.

8.1.1.5 Current Sharing

Current sharing is possible through the use of external operational amplifiers. For more details, see 6A Current-Sharing Dual LDO.

8.1.1.6 Recommended Capacitor Types

The TPS7A85A is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input, output, and noise-reduction pin (NR/SS). Multilayer ceramic capacitors are the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that use X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is not recommended because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and temperature; derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein account for a capacitance derating of approximately 50%, but at high V_IN and V_OUT conditions (for example, V_IN = 5.6 V to V_OUT = 5.1 V) the derating can be greater than 50% and must be taken into consideration.

8.1.1.7 Input and Output Capacitor Requirements (C_IN and C_OUT)

The TPS7A85A is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 μF or greater of capacitance) at the output and 10 µF or greater (5 μF or greater of capacitance) at the input. TI recommends using a capacitor with a value of at least 47 µF at the input to minimize input impedance. Place the input and output capacitors as close as possible to the respective input and output pins to minimize trace parasitic. If the trace inductance from the input supply to the TPS7A85A is high, a fast current transient can cause V_IN to ring above the absolute maximum voltage rating and damage the device. This situation can be mitigated by additional input capacitors to dampen the ringing and to keep it below the device absolute maximum ratings.

A combination of multiple output capacitors boosts the high-frequency PSRR as shown in several of the PSRR curves. The combination of one 0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized,
10-µF ceramic capacitors with a sufficient voltage rating in conjunction with the PSRR boost circuit optimizes PSRR for the frequency range of 400 kHz to 700 kHz, a typical range for dc-dc supply switching frequency. This 47-µF || 10-µF || 10-µF combination also ensures that at high input voltage and high output voltage configurations, the minimum effective capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a voltage derating of approximately 60% to 80% at 5.15 V, so the addition of the two 10-µF capacitors ensures that the capacitance is at or above 25 µF.

8.1.1.8 Feed-Forward Capacitor (C_FF)

Although a feed-forward capacitor (C_FF) from the FB pin to the OUT pin is not required to achieve stability, a
10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher capacitance C_FF can be used; however, the start-up time is longer, and the PG signal can incorrectly indicate that the output voltage is settled. For a detailed description, see Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator.

8.1.1.9 Noise-Reduction and Soft-Start Capacitor (C_NR/SS)

The TPS7A85A features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (C_NR/SS).The use of an external C_NR/SS is highly recommended, especially to minimize inrush current into the output capacitors. This soft-start eliminates power-up initialization problems when powering field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output reduces peak inrush current during start-up, which minimizes start-up transients to the input power bus.

To achieve a monotonic start-up, the TPS7A85A error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start charging current (I_NR/SS), the soft-start capacitance (C_NR/SS), and the internal reference (V_NR/SS). Soft-start ramp time can be calculated with Equation 6:

Equation 6.

I_NR/SS is shown in Electrical Characteristics.

The noise-reduction capacitor (in conjunction with the noise-reduction resistor) forms a low-pass filter (LPF) that minimizes the noise from the reference. The reference and noise are amplified by the error amplifier and so the C_NR/SS reduces the overall noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with Equation 7. The typical value of R_NR/SS is 250 kΩ. Increasing the C_NR/SS capacitor has a dominant effect on the output noise at higher output voltages because of the larger gain that is present on the error amplifier. For low-noise applications, TI recommends using a 10-nF to 1-µF C_NR/SS . A larger C_NR/SS has a higher leakage current and as a result, the start-up time may be higher than the expected soft-start time calculated with Equation 6.

Equation 7.

8.1.2.1 Circuit Soft-Start Control (NR/SS)

Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an external capacitor (C_NR/SS). This soft-start eliminates power-up initialization problems when powering field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output reduces peak inrush current during start-up, which minimizes start-up transients to the input power bus.

The output voltage (V_OUT) rises proportionally to V_NR/SS during start-up as the LDO regulates so that the feedback voltage equals the NR/SS voltage (V_FB = V_NR/SS). The time required for V_NR/SS to reach the nominal value determines the rise time of V_OUT (start-up time).

Not using a noise-reduction capacitor on the NR/SS pin may result in an output voltage overshoot of approximately 10%. Using a capacitor on the NR/SS pin minimizes the overshoot.

lists the soft-start charging current values.

8.1.2.1.1 Inrush Current

Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current consists of the sum of load current and the current that charges the output capacitor. This current is difficult to measure because the input capacitor must be removed, which is not recommended. This soft-start current can be estimated by Equation 8:

Equation 8.

where

• V_OUT(t) is the instantaneous output voltage of the turnon ramp
• dV_OUT(t) / dt is the slope of the V_OUT ramp
• R_LOAD is the resistive load impedance

8.1.2.2 Undervoltage Lockout (UVLO)

The UVLO circuits ensure that the device stays disabled before the input or bias supplies reach the minimum operational voltage range, and ensures that the device properly shuts down when the input or bias supply collapses.

Figure 53 and Table 8 show one of the UVLO circuits triggered by various input voltage events, assuming that V_EN ≥ V_IH(EN).

Figure 53. Typical UVLO Operation

Similar to many other LDOs with this feature, the UVLO circuits take a few microseconds to fully assert. During this time, a downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the UVLO circuits do not have enough stored energy to fully discharge the internal circuits inside of the device. When the UVLO circuits are not given enough time to fully discharge the internal nodes, the outputs are not fully disabled.

The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall time of the input supply when operating near the minimum V_IN.

8.1.2.3 Power-Good (PG) Function

The PG circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The PG circuit asserts whenever FB, V_IN, or EN are below the thresholds. The PG operation versus the output voltage is shown in Figure 54, which is listed in Table 9.

Figure 54. Typical PG Operation

The PG pin is open-drain and connects a pullup resistor to an external supply, enabling other devices to receive power good as a logic signal that can be used for sequencing. Take care to ensure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices.

To ensure proper operation of the PG circuit, the pullup resistor value must be from 10 kΩ and 100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the PG transistor, and the upper limit of 100 kΩ results from the maximum leakage current at the PG node. If the pullup resistor is outside of this range, then the PG signal may not read a valid digital logic level.

Using a large C_FF with a small C_NR/SS causes the PG signal to incorrectly indicate that the output voltage has settled during turnon. The C_FF time constant must be greater than the soft-start time constant to ensure proper operation of the PG during start-up. For a detailed description, see Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator.

The state of PG is only valid when the device operates above the minimum supply voltage. During short brownout events and at light loads, PG does not assert because the output voltage (and as a result, V_FB) is sustained by the output capacitance.

8.1.3.1 Power-Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO control loop rejects signals from V_IN to V_OUT across the frequency spectrum (usually 10 Hz to 10 MHz). Equation 9 gives the PSRR calculation as a function of frequency for the input signal (V_IN(f)) and output signal (V_OUT(f)).

Equation 9.

Although PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for convenience.

A simplified diagram of PSRR versus frequency is shown in Figure 55.

Figure 55. Power-Supply Rejection Ratio Diagram

An LDO is often employed not only as a dc-dc regulator, but provides exceptionally clean power-supply voltages that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for the TPS7A85A.

The TPS7A85A features an innovative circuit to boost the PSRR from 200 kHz to 1 MHz; see . To achieve the maximum benefit of this PSRR boost circuit, TI recommends using a capacitor with a minimum impedance in the 100-kHz to 1-MHz band.

8.1.3.2 Output Voltage Noise

The TPS7A85A is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. For example, the TPS7A85A can be used in a phase-locked loop (PLL)-based clocking circuit can be used for minimum phase noise, or in test and measurement systems where small power-supply noise fluctuations reduce system dynamic range.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions, thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower frequencies as a function of 1/f). Figure 56 shows a simplified output voltage noise density plot versus frequency.

Figure 56. Output Voltage Noise Diagram

For further details, see the How to Measure LDO Noise white paper.

8.1.3.3 Optimizing Noise and PSRR

The ultra-low noise floor and PSRR of the device can be improved in several ways, as listed in Table 10.

The noise-reduction capacitor (in conjunction with the noise-reduction resistor) forms a low-pass filter (LPF) that filters out the noise from the reference before being gained up with the error amplifier, which minimizes the output voltage noise floor. The LPF is a single-pole filter, and the cutoff frequency can be calculated with Equation 10. The typical value of R_NR/SS is 250 kΩ. The effect of the C_NR/SS capacitor increases when V_OUT(nom) increases because the noise from the reference is gained up when the output voltage increases. For low-noise applications, TI recommends a 10-nF to 10-µF C_NR/SS.

Equation 10.

The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feed-forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing out the loop bandwidth, which improves mid-band PSRR.

A larger C_OUT or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing the high-frequency output impedance of the power supply.

Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the internal circuits. However, a high power dissipation across the die increases the output noise because of the increase in junction temperature.

Good PCB layout improves the PSRR and noise performance by providing heat sinking at low frequencies and isolating V_OUT at high frequencies.

Table 11 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5-V output for a variety of conditions with an input voltage of 5.5 V and a load current of 4 A. The 5-V output is selected as a worst-case nominal operation for output voltage noise.

8.1.3.3.1 Charge Pump Noise

The device internal charge pump generates a minimal amount of noise, as shown in Figure 57.

Using a bias rail minimizes the internal charge-pump noise when the internal voltage is clamped, which reduces the overall output noise floor.

The high-frequency components of the output voltage noise density curve are filtered out in most applications by using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the load input capacitors forms a pi-filter, which further reduces the high-frequency noise contribution.

Figure 57. Charge Pump Noise

8.1.3.4 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, where output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure 58 are further described in this section and are listed in Table 12. Regions A, E, and H are where the output voltage is in steady-state.

Figure 58. Load Transient Waveform

The transient response peaks (V_OUT(max) and V_OUT(min)) are improved by using more output capacitance; however, using more output capacitance slows down the recovery time (W_rise and W_fall). Figure 59 shows these parameters during a load transient with a given pulse duration (PW) and current levels (I_OUT(LO) and I_OUT(HI)).

Figure 59. Simplified Load Transient Waveform

8.1.4.1 Output Voltage Accuracy (V_OUT)

The device features an output voltage accuracy of 0.75% maximum with BIAS that includes the errors introduced by the internal reference, load regulation, line regulation, and operating temperature as shown in the . Output voltage accuracy specifies minimum and maximum output voltage error relative to the expected nominal output voltage stated as a percent.

8.1.4.2 Dropout Voltage (V_DO)

Generally, the dropout voltage refers to the minimum voltage difference between the input and output voltage (V_DO = V_IN – V_OUT) that is required for regulation. When V_IN drops below the required V_DO for the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is proportional to the output current because the device is operating as a resistive switch, as shown in Figure 60.

Figure 60. Dropout Voltage versus Output Current

Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect to V_IN on this device because of the internal charge pump. Dropout voltage increases exponentially when the input voltage approaches the maximum operating voltage.

8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation

Some applications can have transients that place the LDO into dropout, such as slower ramps on V_IN for start-up or load transients. As with many other LDOs, the output can overshoot on recovery from these conditions.

A ramping input supply can cause an LDO to overshoot on start-up when the slew rate and voltage levels are in the right range, as shown in Figure 61. This condition is simply avoided by using an enable signal or by increasing the soft-start time with C_SS/NR.

Figure 61. Start-Up Into Dropout

8.1.8.1 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not referencing thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JT and Ψ_JB) are shown in and are used in accordance with Equation 14.

Equation 14.

where

• P_D is the power dissipated as explained in
• T_T is the temperature at the center-top of the device package, and
• T_B is the PCB surface temperature measured 1 mm from the device package and centered on the package edge

8.1.8.2 Recommended Area for Continuous Operation (RACO)

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input voltage. The recommended area for continuous operation for a linear regulator can be separated into the following parts, as shown in Figure 63:

• Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output (V_IN – V_OUT) at a given output current level; see Dropout Voltage (VDO) for more details.
• Limited by rated output current: The rated output current limits the maximum recommended output current level. Exceeding this rating causes the device to fall out of specification.
• Limited by thermals: The shape of the slope is calculated by Equation 14. The slope is nonlinear because the junction temperature of the LDO is controlled by the power dissipation across the LDO. As a result, when V_IN – V_OUT increases, the output current must decrease to ensure that the rated junction temperature of the device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and reduces long-term reliability.
• Limited by V_IN range: The rated input voltage range governs both the minimum and maximum of V_IN – V_OUT.

Figure 63. Continuous Operation Slope Region Description

Figure 64 to Figure 69 show the recommended area of operation curves for this device on a JEDEC-standard, high-K board with a R_θJA = 43.4°C/W, as shown in .

Figure 64. Recommended Area for Continuous Operation for V_OUT = 0.9 V

Figure 66. Recommended Area for Continuous Operation for V_OUT = 1.8 V

Figure 68. Recommended Area for Continuous Operation for V_OUT = 3.3 V

Figure 65. Recommended Area for Continuous Operation for V_OUT = 1.2 V

Figure 67. Recommended Area for Continuous Operation for V_OUT = 2.5 V

Figure 69. Recommended Area for Continuous Operation for V_OUT = 5 V

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 13 as the input parameters.

8.2.1.2 Detailed Design Procedure

At 4 A, the dropout of the TPS7A85A has 240-mV maximum dropout over temperature, and a result, a 400-mV headroom is sufficient for operation over input and output voltage accuracy. The bias rail is provided for better performance for the LILO conditions. The PSRR is greater than 40 dB in these conditions, and noise is less than 10 µV_RMS, as listed in Table 13.

The ANY-OUT internal resistor network is used for maximum accuracy.

The 100mV pin is grounded to achieve 0.9 V on the output. The voltage value of 100 mV is added to the 0.8-V internal reference voltage for V_OUT(nom) equal to 0.9 V, as shown in Equation 15.

Equation 15.

Input and output capacitors are selected in accordance with External Component Selection. Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the output are selected.

To satisfy the required start-up time and still maintain low-noise performance, a 100-nF C_NR/SS is selected. This value is calculated with Equation 16.

Equation 16.

At the 4-A maximum load, the internal power dissipation is 2 W and corresponds to a 7°C junction temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient temperature, the junction temperature is at 62°C. To further minimize noise, a feed-forward capacitance (C_FF) of 10 nF is selected.

8.2.1.3 Application Curves

Figure 71. Output Load Transient Response

Figure 72. Output Start-Up Response