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ZHCSBA4E May 2013 – August 2014 TPS7A8300

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RGR|20
- MPQF239A
RGW|20
- MPQF122C

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RGR|20
- QFND242E
RGW|20
- QFND012L

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over junction temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	IN, BIAS, PG, EN	–0.3	7.0	V
	IN, BIAS, PG, EN (5% duty cycle)	–0.3	7.5	V
	SNS, OUT	–0.3	V_IN + 0.3⁽²⁾	V
	NR/SS, FB	–0.3	3.6	V
	50mV, 100mV, 200mV, 400mV, 800mV, 1.6V	–0.3	V_OUT + 0.3	V
Current	OUT	Internally limited		A
Current	PG (sink current into device)		5	mA
Operating junction temperature, T_J		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The absolute maximum rating is V_IN + 0.3 V or 7.0 V, whichever is smaller.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–55	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2	2	kV
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–500	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input supply voltage range	1.1	6.5	V
V_BIAS	Bias supply voltage range⁽¹⁾	3.0	6.5	V
I_OUT	Output current	0	2	A
T_J	Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS7A8300		UNIT
		RGW (QFN)	RGR (QFN)
		20 PINS	20 PINS
R_θJA	Junction-to-ambient thermal resistance	33.6	35.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	30.0	47.6
R_θJB	Junction-to-board thermal resistance	14.0	12.3
ψ_JT	Junction-to-top characterization parameter	0.2	0.5
ψ_JB	Junction-to-board characterization parameter	14.0	12.4
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.6	1.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over operating temperature range (T_J = –40°C to 125°C), {1.1 V ≤ V_IN < 1.4 V and 3.0 V ≤ V_BIAS ≤ 6.5 V} or {V_IN ≥ 1.4 V and V_BIAS open}⁽¹⁾, V_IN ≥ V_OUT(TARGET) + 0.3 V⁽²⁾, V_OUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND⁽³⁾, V_EN = 1.1 V, C_OUT =
22 μF, C_NR/SS = 0 nF, C_FF = 0 nF, and PG pin pulled up to V_IN with 100 kΩ, unless otherwise noted.
Typical values are at T_J = 25°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IN	Input supply voltage range		1.1		6.5	V
V_BIAS	Bias supply voltage range⁽¹⁾		3.0		6.5	V
V_(REF)	Reference voltage	V_(REF) = V_(FB) = V_(NR/SS)		0.8		V
V_UVLO1(IN)	Input supply UVLO with BIAS	V_IN increasing		1.02	1.085	V
V_HYS1(IN)	V_UVLO1(IN) hysteresis			320		mV
V_UVLO2(IN)	Input supply UVLO without BIAS	V_IN increasing		1.31	1.39	V
V_HYS2(IN)	V_UVLO2(IN) hysteresis			253		mV
V_UVLO(BIAS)	Bias supply UVLO	V_BIAS increasing		2.83	2.9	V
V_HYS(BIAS)	V_UVLO(BIAS) hysteresis			290		mV
V_OUT	Output voltage range	Using voltage setting pins (50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V)	0.8 – 1.0%		3.95 + 1.0%	V
	Output voltage range	Using external resistors	0.8 – 1.0%		5.0 + 1.0%	V
	Output voltage accuracy⁽⁴⁾⁽⁵⁾	0.8 V ≤ V_OUT ≤ 5 V, 5 mA ≤ I_OUT ≤ 2 A	–1.0%		1.0%
	Output voltage accuracy⁽⁴⁾⁽⁵⁾	V_IN = 1.5 V, V_OUT = 1.2 V, 5 mA ≤ I_OUT ≤ 1.2 A	–1.0%		1.0%
ΔV_O(ΔVI)	Line regulation	I_OUT = 5 mA, 1.4 V ≤ V_IN ≤ 6.5 V		0.003		%/V
ΔV_O(ΔIO)	Load regulation	5 mA ≤ I_OUT ≤ 2 A		0.0001		%/A
V_(DO)	Dropout voltage	V_IN ≥ 1.4 V and V_BIAS open, 0.8 V ≤ V_OUT ≤ 5.0 V, I_OUT = 2 A, V_FB = 0.8 V – 3%			200	mV
V_(DO)	Dropout voltage	V_IN = 1.1 V, V_BIAS = 5.0 V, V_OUT(TARGET) = 0.8 V, I_OUT = 2 A, V_FB = 0.8 V – 3%			125	mV
I_(LIM)	Output current limit	V_OUT forced at 0.9 × V_OUT(TARGET), V_IN = V_OUT(TARGET) + 300 mV	2.1	3.4	4.2	A
I_(GND)	GND pin current	Minimum load, V_IN = 6.5 V, no V_BIAS supply, I_OUT = 5 mA		2.8	4	mA
		Maximum load, V_IN = 1.4 V, no V_BIAS supply, I_OUT = 2 A		3.7	5	mA
		Shutdown, PG = (open), V_IN = 6.5 V, no V_BIAS supply, V_(EN) = 0.5 V			2.5	μA
I_(EN)	EN pin current	V_IN = 6.5 V, no V_BIAS supply, V_(EN) = 0 V and 6.5 V	–0.1		0.1	μA
I_(BIAS)	BIAS pin current	V_IN = 1.1 V, V_BIAS = 6.5 V, V_OUT(TARGET) = 0.8 V, I_OUT = 2 A		2.3	3.5	mA
V_IL(EN)	EN pin low-level input voltage (disable device)		0		0.5	V
V_IH(EN)	EN pin high-level input voltage (enable device)		1.1		6.5	V
V_IT(PG)	PG pin threshold	For the direction PG↓ with decreasing V_OUT	0.82 V_OUT	0.872 V_OUT	0.93 V_OUT	V
V_hys(PG)	PG pin hysteresis	For PG↑		0.02 V_OUT		V
V_OL(PG)	PG pin low-level output voltage	V_OUT < V_IT(PG), I_PG = –1 mA (current into device)			0.4	V
I_lkg(PG)	PG pin leakage current	V_OUT > V_IT(PG), V_(PG) = 6.5 V			1	μA
I_(NR/SS)	NR/SS pin charging current	V_NR/SS = GND, V_IN = 6.5 V	4.0	6.2	9.0	μA
I_FB	FB pin leakage current	V_IN = 6.5 V	–100		100	nA
PSRR	Power-supply ripple rejection	f = 1 MHz, V_IN = 3.8 V, V_OUT = 3.3 V, I_OUT = 2 A, C_NR/SS = 10 nF, C_FF = 10 nF		40		dB
V_n	Output noise voltage	BW = 10 Hz to 100 kHz, V_IN = 1.4 V, V_OUT = 0.8 V, I_OUT = 1.5 A, C_NR/SS = 10 nF, C_FF = 10 nF		6		μV_RMS
T_sd	Thermal shutdown temperature	Shutdown, temperature increasing		160		°C
T_sd	Thermal shutdown temperature	Reset, temperature decreasing		140		°C
T_J	Operating junction temperature		–40		125	°C

(1) BIAS supply is required when the V_IN supply is below 1.4 V. Conversely, no BIAS supply is needed when the V_IN supply is higher than or equal to 1.4 V.

(2) V_OUT(TARGET) is the calculated V_OUT target value from the output voltage setting pins: 50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V in a fixed configuration. In an adjustable configuration, V_OUT(TARGET) is the expected V_OUT value set by the external feedback resistors.

(3) This 50-Ω load is disconnected when the test conditions specify an I_OUT value.

(4) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(5) The device is not tested under conditions where V_IN > V_OUT + 2.5 V and I_OUT = 2 A, because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.

6.6 Typical Characteristics

At T_J = 25°C, {1.1 V ≤ V_IN < 1.4 V and 3.0 V ≤ V_BIAS ≤ 6.5 V} or {V_IN ≥ 1.4 V and V_BIAS open}

(1) BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is needed when the VIN supply is higher than or equal to 1.4 V.

, V_IN ≥ V_OUT(TARGET) + 0.3 V, V_OUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, V_EN = 1.1 V, C_OUT = 22 μF, C_NR/SS = 0 nF, C_FF = 10 nF, and PG pin pulled up to V_IN with 100 kΩ, unless otherwise noted.

V_OUT(TARGET) = 0.8 V, I_OUT = 5 mA, V_BIAS = Open

Figure 1. Minimum ANY-OUT V_OUT Line Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 3. Minimum ANY-OUT V_OUT, Minimum V_IN, No BIAS Load Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, I_OUT = 5 mA

Figure 5. Minimum ANY-OUT V_OUT, Minimum V_IN BIAS
Line Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 6.5 V

Figure 7. Minimum Adjustable V_OUT, Minimum V_IN,
Maximum BIAS Load Regulation

V_OUT(TARGET) = 5 V, I_OUT = 5 mA, V_BIAS = Open

Figure 9. Maximum Adjustable V_OUT, No BIAS
Line Regulation

V_OUT(TARGET) = 5 V, V_IN = 5.3 V, V_BIAS = Open

Figure 11. Maximum Adjustable V_OUT Load Regulation

V_IN = 5.5 V, ANY-OUT, V_BIAS = Open,

Figure 13. Dropout Voltage vs Output Current

V_BIAS = Open, I_OUT = 2 A, ANY-OUT

Figure 15. Dropout Voltage vs Input Voltage

V_IN = 1.1 V, ANY-OUT, I_OUT = 2 A

Figure 17. Minimum V_IN Dropout Voltage vs Bias Voltage

V_OUT(TARGET) = 0.8 V, I_OUT = 5 mA, V_IN = 1.1 V

Figure 19. Minimum ANY-OUT V_OUT, Minimum V_IN
Quiescent Current vs Bias Voltage

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 3 V

Figure 21. Minimum ANY-OUT V_OUT, V_IN, and BIAS
Quiescent Current vs Output Current

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V

Figure 23. Minimum ANY-OUT V_OUT, Minimum V_IN
Shutdown Current vs Bias Voltage

V_IN = 1.8 V, ANY-OUT, V_BIAS = Open, V_OUT(TARGET) = 1.5 V

Figure 25. Current Limit vs Output Voltage

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 3 V

Figure 27. Minimum ANY-OUT V_OUT, V_IN, and BIAS
Current Limit vs Output Voltage

V_OUT(TARGET) = 0.8 V, V_BIAS = 3.0 V

Figure 29. Minimum ANY-OUT V_OUT, Minimum BIAS
Input UVLO Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V

Figure 31. Minimum ANY-OUT V_OUT, Minimum V_IN BIAS
UVLO Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = 6.5 V, V_BIAS = Open

Figure 33. Minimum ANY-OUT V_OUT, Maximum V_IN
Enable Threshold vs Temperature

V_IN = 6.5 V, V_OUT(TARGET) = 0.8 V, V_BIAS = Open

Figure 35. Minimum ANY-OUT V_OUT, Maximum V_IN, No BIAS PG Low Voltage vs PG Current

V_OUT(TARGET) = 0.8 V, V_IN = 6.5 V, V_BIAS = Open

Figure 37. Minimum ANY-OUT V_OUT, Maximum V_IN
PG Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = V_PG = 6.5 V, V_BIAS = Open

Figure 39. Minimum ANY-OUT V_OUT, Maximum V_IN
PG Current vs Temperature

V_OUT(TARGET) = 3.3 V, ANY-OUT, V_IN = V_EN = 3.8 V, V_BIAS = Open, I_OUT = 1.5 A, C_OUT = 22 µF, C_FF = 10 nF

Figure 41. Power-Supply Rejection vs C_NR/SS

V_IN = V_OUT(TARGET) + 0.5 V, ANY-OUT, V_BIAS = Open, I_OUT = 1.5 A, C_OUT = 22 µF, C_NR/SS = C_FF = 10 nF

Figure 43. Spectral Noise Density vs Output Voltage

V_IN = 3.8 V, V_OUT(TARGET) = 3.3 V, ANY-OUT, V_BIAS = Open,
I_OUT = 1.5 A, C_OUT = 22 µF, C_NR/SS = 10 nF

Figure 45. Spectral Noise Density vs C_FF

V_IN = 1.4 V, V_OUT = 0.8 V, C_NR/SS = 0 nF

Figure 47. Start-Up (C_NR/SS = 0 nF)

V_IN = 1.4 V to 6 V to 1.4 V at 1 V/µs,
V_OUT = 0.8 V, I_OUT = 2 A, C_NR/SS = C_FF = 10 nF

Figure 49. Line Transient

V_OUT(TARGET) = 3.95 V, I_OUT = 5 mA, V_BIAS = Open

Figure 2. Maximum ANY-OUT V_OUT Line Regulation

V_OUT(TARGET) = 3.95 V, V_IN = 4.25 V, V_BIAS = Open

Figure 4. Maximum ANY-OUT V_OUT Load Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 3 V

Figure 6. Minimum ANY-OUT V_OUT, V_IN, and BIAS
Load Regulation

V_OUT(TARGET) = 0.8 V, I_OUT = 5 mA, V_BIAS = Open

Figure 8. Minimum Adjustable V_OUT, No BIAS
Line Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 10. Minimum Adjustable V_OUT, Minimum V_IN,
No BIAS Load Regulation

V_IN = 1.4 V, ANY-OUT, V_BIAS = Open, No BIAS

Figure 12. Minimum V_IN Dropout Voltage vs Output Current

V_BIAS = Open, I_OUT = 0.5 A, ANY-OUT

Figure 14. Dropout Voltage vs Input Voltage

V_IN = 1.1 V, ANY-OUT, I_OUT = 0.5 A

Figure 16. Dropout Voltage vs Bias Voltage

V_OUT(TARGET) = 0.8 V, I_OUT = 5 mA, V_BIAS = Open

Figure 18. Minimum ANY-OUT V_OUT, No BIAS
Quiescent Current vs Input Voltage

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 20. Minimum ANY-OUT V_OUT, Minimum V_IN, No BIAS Quiescent Current vs Output Current

V_OUT(TARGET) = 0.8 V, V_BIAS = Open

Figure 22. Minimum ANY-OUT V_OUT, No BIAS
Shutdown Current vs Input Voltage

V_OUT(TARGET) = 0.8 V, V_BIAS = Open

Figure 24. Minimum ANY-OUT V_OUT, No BIAS
Soft-Start Current vs Input Voltage

V_OUT(TARGET) = 3.95 V, V_IN = 4.25 V, V_BIAS = Open

Figure 26. Maximum ANY-OUT V_OUT
Current Limit vs Output Voltage

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 6.5 V

Figure 28. Minimum ANY-OUT V_OUT, Minimum V_IN,
Maximum BIAS Current Limit vs Output Voltage

V_OUT(TARGET) = 0.8 V, V_BIAS = Open

Figure 30. Minimum ANY-OUT V_OUT, No BIAS
Input UVLO Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 32. Minimum ANY-OUT V_OUT, Minimum V_IN, No BIAS Enable Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = V_EN = 6.5 V, V_BIAS = Open

Figure 34. Minimum ANY-OUT V_OUT, Maximum V_IN
Enable Current vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 36. Minimum ANY-OUT V_OUT, Minimum V_IN, No BIAS PG Low Voltage vs PG Current

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 38. Minimum ANY-OUT V_OUT, Maximum V_IN, No BIAS PG Threshold vs Temperature

V_OUT(TARGET) = 3.3 V, ANY-OUT, V_IN = V_EN = 3.8 V, V_BIAS = Open, C_OUT = 22 µF, C_NR/SS = C_FF = 10 nF

Figure 40. Power-Supply Rejection vs Output Current

V_OUT(TARGET) = 1.2 V, ANY-OUT, V_BIAS = Open, I_OUT = 1.5 A, C_OUT = 22 µF, C_NR/SS = C_FF = 10 nF

Figure 42. Power-Supply Rejection vs Input Voltage

V_IN = 3.8 V, V_OUT(TARGET) = 3.3 V, ANY-OUT, V_BIAS = Open,
I_OUT = 1.5 A, C_OUT = 22 µF, C_FF = 10 nF

Figure 44. Spectral Noise Density vs C_NR/SS

V_IN = 3.85 V, V_OUT = 3.3 V, I_OUT = 100 mA to 1 A to 100 mA at 1 A/µs, C_O = 22 µF

Figure 46. Load Transient Response

V_IN = 1.4 V, V_OUT = 0.8 V, C_NR/SS = 10 nF

Figure 48. Start-Up