ZHCS599B December 2011 – August 2015 TPS7A8101
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRB|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRB|8
訂購信息
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A8101 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) at very low headroom (VIN – VOUT). A noise reduction capacitor (CNR) at the NR pin and a bypass capacitor (CBYPASS) bypass noise generated by the bandgap reference to improve PSRR, while a quick-start circuit fast-charges the noise reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C.
8.1.1 Recommended Component Values
Table 1. Recommended Capacitor Values
| SYMBOL | NAME | VALUE |
|---|---|---|
| CIN | Input capacitor | 10 µF |
| COUT | Output capacitor | 10 µF |
| CNR | Noise reduction capacitor between NR and GND | 470 nF |
| CBYPASS | Noise reduction capacitor across R1 | 470 nF |
Table 2. Recommended Feedback Resistor Values for Common Output Voltages
| VOUT | R1 | R2 |
|---|---|---|
| 0.8 V | 0 Ω (Short) | 10 kΩ |
| 1 V | 2.49 kΩ | 10 kΩ |
| 1.2 V | 4.99 kΩ | 10 kΩ |
| 1.5 V | 8.87 kΩ | 10 kΩ |
| 1.8 V | 12.5 kΩ | 10 kΩ |
| 2.5 V | 21 kΩ | 10 kΩ |
| 3.3 V | 30.9 kΩ | 10 kΩ |
| 5 V | 52.3 kΩ | 10 kΩ |
8.2 Typical Application
Figure 31 illustrates the connections for the device.
Figure 31. Typical Application Circuit
8.2.1 Design Requirements
8.2.1.1 Dropout Voltage
The TPS7A8101 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device in dropout behaves the same way as a resistor.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 19 and Figure 20 in the Typical Characteristics section.
8.2.1.2 Minimum Load
The TPS7A8101 is stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS7A8101 employs an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current.
8.2.1.3 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.
The TPS7A8101 is designed to be stable with standard ceramic capacitors of capacitance values 4.7 μF or larger. This device is evaluated using a 10-μF ceramic capacitor of 10-V rating, 10% tolerance, X5R type, and 0805 size (2 mm × 1.25 mm).
X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 1 Ω.
8.2.2 Detailed Design Procedure
The voltage on the FB pin sets the output voltage and is determined by the values of R1 and R2. The values of R1 and R2 can be calculated for any voltage using the formula given in Equation 2:
Table 2 shows sample resistor values for common output voltages. In Table 2, E96 series resistors are used, and all values meet 1% of the target VOUT, assuming resistors with zero error. For the actual design, pay attention to any resistor error factors. Using lower values for R1 and R2 reduces the noise injected from the FB pin.
8.2.2.1 Output Noise
In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS7A8101, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. If a bypass capacitor (CBYPASS) across the high-side feedback resistor (R1) is used with the TPS7A8101 in addition to CNR, noise from these other sources can also be significantly reduced.
To maximize noise performance in a given application, use a 0.47-μF noise-reduction capacitor plus a 0.47-μF bypass capacitor.
8.2.2.2 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration of the transient response. Line transient performance can be improved by using a larger noise reduction capacitor (CNR) and/or bypass capacitor (CBYPASS).
8.2.3 Application Curve
