ZHCSHB6A November 2019 – March 2020 TPS7A53
PRODUCTION DATA.
The TPS7A53EVM is used to develop the TPS7A5401RPS thermal model. The RPS package is a 2.2-mm × 2.5-mm, 12-pin VQFN with 25-µm plating on each via. The EVM is a 3-inch by 3-inch (7.62 mm × 7.62 mm) PCB comprised of four layers. Table 6 lists an overview of the EVM stackup. Figure 48 to Figure 52 provide layer details for the EVM.
| LAYER | NAME | MATERIAL | THICKNESS (mil) |
|---|---|---|---|
| 1 | Top overlay | — | — |
| 2 | Top solder | Solder resist | 0.40 |
| 3 | Top layer | Copper | 1.40 |
| 4 | Dielectric 1 | FR-4, high TG | 18.50 |
| 5 | Mid layer 1 | Copper | 1.40 |
| 6 | Dielectric 2 | FR-4, high TG | 18.60 |
| 7 | Mid layer 2 | Copper | 1.40 |
| 8 | Dielectric 3 | FR-4, high TG | 18.50 |
| 9 | Bottom layer | Copper | 1.40 |
| 10 | Bottom solder | Solder resist | 0.40 |
Figure 53 shows the thermal gradient on the PCB that results when a 1-W power dissipation is used through the PassFET with a 25°C ambient temperature.
Figure 53. PCB Thermal Gradient For additional information on the PCB, see the TPS7A53EVM user guide.