ZHCS831E march 2012 – may 2023 TPS7A16-Q1
PRODUCTION DATA
The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY) connected from the DELAY pin to GND; this capacitor is charged from 0 V to approximately 1.8 V by the DELAY pin current (IDELAY) when VOUT exceeds the PG trip threshold (VIT).