4 Revision History
Changes from Revision S (August 2022) to Revision T (December 2022)
- 向文檔中添加了 M3 器件的信息(新芯片信息)Go
- 更改了特性 部分:更改了可調輸出電壓選項,將額定結溫 更改為工作結溫,并重新排列了特性 要點Go
- 向首頁添加了靜態電流與負載電流 曲線Go
- 刪除了說明 部分中的低功率級別討論Go
- 更改了典型應用原理圖
Go
- Changed Pin Functions table: changed Description
column and added footnoteGo
- Added condition statement and characterization conditions plots to
Typical Characteristics sectionGo
- Changed curve titles in Typical Characteristics section to
distinguish between new and legacy chipsGo
- Changed block diagrams in Functional Block Diagrams
sectionGo
- Changed Low Quiescent Current section and titleGo
- Deleted thermal shutdown discussion from Current Limit
sectionGo
- Changed third bullet in Normal Operation
sectionGo
- Changed Application Information sectionGo
- Changed Typical Application sectionGo
- Changed output operating voltage range from 1.2 V to 15 V to
1.205 V to 15 V in Setting VOUT for the TPS71501 Adjustable
LDO
Go
- Added reverse current limit discussion to Reverse Current
sectionGo
- Changed Application Curves section Go
- Deleted sentence stating This input supply must be well
regulated from Power Supply Recommendations
sectionGo
- Changed Example Layout for the TPS71501DCK
figureGo
- Changed Device Nomenclature tableGo
Changes from Revision R (February 2015) to Revision S (August 2022)
- 更新了整個文檔中的表格、圖和交叉參考的編號格式Go
- 更改了文檔標題Go
- 更改了特性 部分Go
- 更改了應用 部分Go
- 更改了說明 部分Go
- Changed descriptions of FB and NC pins in Pin Functions
table, split fixed and adjustable pin outs apart Go
- Added new chip specific plots to Typical Characteristics
sectionGo
- Changed Overview sectionGo
- Changed block diagrams in Functional Block Diagrams
sectionGo
- Changed Low Quiescent Current section and titleGo
- Changed Dropout Voltage (VDO)
sectionGo
- Deleted Disabled row from Device Functional Mode
Comparison tableGo
- Changed Dropout Operation sectionGo
- Changed External Capacitor Requirements
sectionGo
- Added Input and Output Capacitor
Requirements sectionGo
- Changed Reverse Current sectionGo
- Changed output voltage value when no
CFF is used from 0.8 V to 1.205 V
Go
- Added Power Dissipation
(PD) sectionGo
- Added new chip specific plots to Application Curves
sectionGo
- Added second row and deleted second footnote from Device
Nomenclature tableGo