ZHCSDS8E March 2015 – August 2021 TPS65982
PRODUCTION DATA
The TPS65982 has three I2C interface ports. I2C Port 1 is comprised of the I2C_SDA1, I2C_SCL1, and I2C_IRQ1Z pins. I2C Port 2 is comprised of the I2C_SDA2, I2C_SCL2, and I2C_IRQ2Z pins. These interfaces provide general status information about the TPS65982, as well as the ability to control the TPS65982 behavior, as well as providing information about connections detected at the USB-C receptacle and supporting communications to and from a connected device, cable supporting BMC USB-PD, or both. The third port is comprised of the DEBUG_CTL1 and DEBUG_CTL2 pins. This third port is a firmware emulated I2C master. The pins are generic GPIO and do not contain any dedicated hardware for I2C such as detecting starts, stops, acks, or other protocol normally associated with I2C. This third port is always a master and has no interrupt. This port is intended to master another device that has simple control based on mode and multiplexer orientation. DEBUG_CTL1 is the serial clock and DEBUG_CTL2 is serial data.
The first two ports can be a master or a slave, but the default behavior is to be a slave. Port 1 and Port 2 are interchangeable. Each port operates the same way and has the same access in and out of the core. An interrupt mask is set for each that determines what events are interrupted on that given port.