SWCS071C August 2012 – August 2017
PRODUCTION DATA.
Figure 4-1 shows the 81-Pin YFF Die-Size Ball-Grid Array pin assignments.
Figure 4-1 81-Pin YFF DSBGA (Bottom View)
| TERMINAL | TYPE | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | ALT NAME | NO. | ||
| REFERENCE | ||||
| VREF1V25 | H3 | O | Internal reference voltage. Connect a 100-nF capacitor from this pin to GND. Do not load this pin externally. | |
| AGND | F3, C7 | – | Analog ground connection; connect to PGND on the PCB | |
| DRIVERS / LIGHTING | ||||
| LEDA/GPIO3 | B3 | I/O | General-purpose I/O or LED driver output | |
| LEDB/GPIO4 | B2 | I/O | General-purpose I/O or LED driver output | |
| LEDC/GPIO5 | B1 | I/O | General-purpose I/O or LED driver output | |
| STEP-DOWN CONVERTERS | ||||
| VINDCDC_ANA | C8 | I | Analog supply input for DC-DC converters; must be connected to VINDCDC1, VINDCDC2, VINDCDC3 and VINDCDC4 | |
| VINDCDC1 | H7, J7 | I | Power input to DCDC1 converter; connect to VINDCDC2, VINDCDC3, VINDCDC4 and VINDCDC_ANA | |
| VDCDC1 | J4 | I | Voltage sense (feedback) input "+" for DCDC1 | |
| VDCDC1_GND | H4 | I | Voltage sense (feedback) input GND for DCDC1; tie to the GND plane or to AGND, alternatively tie to the GND-pad of the output capacitor | |
| SW1 | H6, J6 | O | Switch node of DCDC1; connect output inductor | |
| PGND1 | H5, J5 | – | Power GND connection for DCDC1 converter | |
| VCON_PWM | F4 | I | PWM period signal for dynamic voltage scaling on DCDC1 | |
| VCON_CLK | F5 | I | Clock signal for dynamic voltage scaling on DCDC1 | |
| VINDCDC2 | C9 | I | Power input to DCDC2 converter; connect to VINDCDC1, VINDCDC3, VINDCDC4 and VINDCDC_ANA | |
| VDCDC2 | D7 | I | Voltage sense (feedback) input for DCDC2 | |
| SW2 | D9 | O | Switch node of DCDC2; connect output inductor | |
| PGND2 | E9 | – | Power GND connection for DCDC2 converter | |
| VINDCDC3 | C1 | I | Power input to DCDC3 converter; connect to VINDCDC1, VINDCDC2, VINDCDC4 and VINDCDC_ANA | |
| VDCDC3 | F2 | I | Voltage sense (feedback) input for DCDC3 | |
| SW3 | D1 | O | Switch node of DCDC3; connect output inductor | |
| PGND3 | E1 | – | Power GND connection for DCDC3 converter | |
| VINDCDC4 | A7, B7 | I | Power input to DCDC4 converter; connect to VINDCDC1, VINDCDC2, VINDCDC3 and VINDCDC_ANA | |
| VDCDC4 | A4 | I | Voltage sense (feedback) input "+" for DCDC4 | |
| VDCDC4_GND | B4 | I | Voltage sense (feedback) input GND for DCDC4; tie to the GND plane or to AGND, alternatively tie to the GND-pad of the output capacitor | |
| SW4 | A6, B6 | O | Switch node of DCDC4; connect output inductor | |
| PGND4 | A5, B5 | – | Power GND connection for DCDC4 converter | |
| LOAD SWITCH | ||||
| LSI | B8, B9 | I | Input of the load switch | |
| LSO | A8, A9 | O | Output of the load switch | |
| EN_LS0 | C3 | I | Load switch enable pin; the status is copied to Bit [LOADSWITCH:ENABLE0] in state CONFIG | |
| EN_LS1 | C2 | I | Load switch enable pin; the status is copied to Bit [LOADSWITCH:ENABLE1] in state CONFIG | |
| LOW DROPOUT REGULATORS | ||||
| VINLDO1210 | J2 | I | Power input for LDO1, LDO2 and LDO10 | |
| VINLDO3 | F8 | I | Power input for LDO3 | |
| VINLDO4 | F1 | I | Power input for LDO4 | |
| VINLDO5 | G8 | I | Power input for LDO5 | |
| VINLDO67 | A2 | I | Power input for LDO6 and LDO7 | |
| VINLDO8 | H8 | I | Power input for LDO8 | |
| VINLDO9 | J8 | I | Power input for LDO9 | |
| LDOAO | G3 | O | "LDO always on" internal supply; connect buffer capacitor | |
| VLDO1 | J3 | O | LDO1 output | |
| VLDO2 | H1 | O | LDO2 output | |
| VLDO3 | F9 | O | LDO3 output | |
| VLDO4 | G1 | O | LDO4 output | |
| VLDO5 | G9 | O | LDO5 output | |
| VLDO6 | A3 | O | LDO6 output | |
| VLDO7 | A1 | O | LDO7 output | |
| VLDO8 | H9 | O | LDO8 output | |
| VLDO9 | J9 | O | LDO9 output | |
| VLDO10 | J1 | O | LDO10 output | |
| STANDARD INTERFACE | ||||
| DEF_SPI_I2C-GPIO | E7 | I | Digital input that defines whether SPI or I2C and GPIOs is available on pins C4, D4, E4, D5: 0=SPI; 1=I2C and GPIO1 and GPIO2 | |
| SCL_SCK | SCK | D5 | I | I2C SCL for DEF_SPI_I2C=1 or SPI SCK for DEF_SPI_I2C=0 |
| SDA_MOSI | MOSI | E4 | I/O | I2C SDA for DEF_SPI_I2C=1 or SPI MASTER OUT SLAVE IN (MOSI) for DEF_SPI_I2C=0 |
| GPIO1_MISO | MISO | D4 | I/O | GPIO1 for DEF_SPI_I2C=1 or SPI MASTER IN SLAVE OUT (MISO) for DEF_SPI_I2C=0 |
| GPIO2_ CE | CE | C4 | I/O | GPIO2 for DEF_SPI_I2C=1 or SPI CHIP ENABLE (CE) active HIGH for DEF_SPI_I2C=0 |
| ENABLE / VOLTAGE SCALING | ||||
| EN1 / DCDC1_SEL(1) | DCDC1_SEL | E8 | I | Enable pin or voltage scaling pin changing the output of a converter or a group of converters between 2 predefined values |
| EN2 / DCDC2_SEL(1) | DCDC2_SEL | D8 | I | Enable pin or voltage scaling pin changing the output of a converter or a group of converters between 2 predefined values |
| EN3 / DCDC3_SEL(1) | DCDC3_SEL | C6 | I | Enable pin or voltage scaling pin changing the output of a converter or a group of converters between 2 predefined values |
| EN4 / DCDC4_SEL(1) | DCDC4_SEL | C5 | I | Enable pin or voltage scaling pin changing the output of a converter or a group of converters between 2 predefined values |
| SCL_AVS / CLK_REQ1(2) | CLK_REQ1 | E5 | I | Power I2C for dynamic voltage scaling: clock pin or clock request signal1 used to enable and disable power resources |
| SDA_AVS / CLK_REQ2(2) | CLK_REQ2 | E6 | I/O | Power I2C for dynamic voltage scaling; data pin or clock request signal2 used to enable and disable power resources |
| SLEEP / PWR_REQ(2) | PWR_REQ | G4 | I | SLEEP mode input or CLK request input |
| nRESPWRON / VSUP_OUT | VSUP_OUT | G6 | O | Reset output or output of voltage monitor |
| VCCS / VIN_MON | VIN_MON | G2 | I | Voltage sense for input voltage monitor; output on pin VSUP_OUT |
| PWRHOLD_ON | ON | D6 | I | POWERHOLD or ON; enable input |
| INT1 | G5 | O | Interrupt output | |
| nPWRON | /RESIN (optional) | D3 | I | Active low, debounced power-on input or power-request input to start power-up sequencing; alternatively active-low reset input to TPS65912x; debounced by 10 ms (OTP option); tie to LDOAO for a logic high if not used. |
| OMAP_WDI_32k_OUT | F6 | I | Input from OMAP WDI pin to AND gate; alternatively 32-kHz RC oscillator output | |
| CPCAP_WDI | G7 | O | Push-pull output at VDDIO level of AND gate; connect to CPCAP WDI input | |
| CONFIG1 | E2 | I | Selects predefined startup options and default voltages; chooses from two internal OTP settings; tie to GND or LDOAO | |
| CONFIG2 | D2 | I | Selects predefined startup options; configures pins as DCDC1_SEL, DCDC2_SEL, DCDC3_SEL and DCDC4_SEL as well as CLK_REQ and PWR_REQ signals with CONFIG2 tied to GND. Tie to LDOAO for a logic high level. | |
| VCC | H2 | I | Digital supply input | |
| VDDIO | F7 | I | Supply voltage input for GPIOs and output stages that sets the HIGH level voltage (I/O voltage) | |
| DGND | E3 | – | Digital GND connection, tie to AGND and PGNDx on the PCB | |