8.5.1 Serial Interface

The serial interface is compatible with the standard and fast mode I²C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above the UVLO threshold. The TPS6572x has a 7-bit address: 100 1000, other addresses are available upon contact with the factory. Attempting to read data from register addresses not listed in this section will result in 00h being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS6572x device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS6572x device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS6572x device must leave the data line high to enable the master to generate the stop condition.

For the WQFN version, the voltage the pull-up resistors for the I²C interface at SCLK and SDAT are connected to, should be monitored by the reset circuitry. This is done by connecting THRESHOLD with a voltage divider to the voltage the SDAT and SCLK pins are pulled-up to. This is needed to ensure a falling supply voltage will cause a reset to the I²C interface. Otherwise a START condition may be detected and the first access to the I²C interface may return NO ACK (no acknowledge).

Figure 18. Bit Transfer on the Serial Interface

Figure 19. START and STOP Conditions

Figure 20. Serial I/f WRITE to TPS6572x Device

Figure 21. Serial I/f READ From TPS6572x: Protocol A

Figure 22. Serial I/f READ From TPS6572x: Protocol B