Table 3. Design Requirements

8.2.1.2.1 Switching Frequency Selection for the Buck Regulator

The first step is to decide on a switching frequency for the regulator. Typically, the user selects the highest switching frequency possible because this produces the smallest solution size. The high switching frequency allows for lower-valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The selectable switching frequency is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage, and the frequency-shift limitation.

Consider minimum on-time and frequency-shift protection as calculated with Equation 4 and Equation 5. To find the maximum switching frequency for the regulator, select the lower value of the two results. Switching frequencies higher than these values result in pulse skipping or the lack of overcurrent protection during a short circuit. The typical minimum on-time, t_ON-min, is 100 ns for the TPS65320D-Q1 device. For this example, where the output voltage is 5 V and the maximum input voltage is 16 V, use a switching frequency of 2000 kHz. Use Equation 3 to calculate the timing resistance for a given switching frequency. The R4 resistor sets the switching frequency. A 2.2-MHz switching frequency requires a 52.45-kΩ resistor (see R4 in Figure 17).

8.2.1.2.2 Output Inductor Selection for the Buck Regulator

Use Equation 22 to calculate the minimum value of the output inductor. The output capacitor filters the inductor ripple current. Therefore, selecting high inductor-ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple-current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines can be used to select this value. K_IND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.

Equation 22.

For designs using low-ESR output capacitors such as ceramics, use a value as high as K_IND = 0.3. When using higher-ESR output capacitors, K_IND = 0.2 yields better results. In a wide-input voltage regulator, selecting an inductor ripple current on the larger side is best because it allows the inductor to still have a measurable ripple current with the input voltage at a minimum.

For this design example, use K_IND = 0.3 and the minimum inductor value which is calculated as 2.24 µH. The nearest standard value would be 2.7 µH. However, in order to support potentially lower switching frequencies or lower ripple, 3.3 µH was chosen (see L1 in Figure 17). Use Equation 23 to calculate the inductor ripple current (I_ripple). For the output filter inductor, do not to exceed the RMS-current and saturation-current ratings. Use Equation 24 and Equation 25 to calculate the RMS current (I_L-RMS) and the peak inductor (I_L-peak).

Equation 23.

Equation 24.

Equation 25.

For this design, the RMS inductor current is 3.21 A, the peak inductor current is 3.52 A, and the inductor ripple current is 0.65 A. The selected inductor is a Coilcraft XAL4030-332MEB, which has a saturation-current rating of 5.5 A and an RMS-current rating of 5 A. As the equation set demonstrates, lower ripple current reduces the output ripple voltage of the buck regulator but requires a larger value of inductance. Selecting higher ripple currents increases the output ripple voltage of the buck regulator but allows for a lower inductance value.

8.2.1.2.3 Output Capacitor Selection for the Buck Regulator

Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output ripple voltage, and how the buck regulator responds to a large change in load current. Select the output capacitance based on the most stringent of these three criteria. The desired response to a large change in the load current is the first criterion. The output capacitor must supply the load with current when the regulator cannot. This situation occurs if the desired hold-up times are present for the buck regulator. In this case, the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily unable to supply sufficient output current if a large, fast increase occurs affecting the current requirements of the load, such as a transition from no load to full load. The buck regulator usually requires two or more clock cycles for the control loop to notice the change in load current and output voltage, and to adjust the duty cycle to react to the change. Size the output capacitor to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable amount of droop in the output voltage. Use Equation 26 to calculate the minimum output capacitance required to supply the difference in current.

Equation 26.

where

• ΔI_O is the change in the buck-regulator output current
• ƒ_S is the switching frequency of the buck regulator
• ΔV_O is the allowable change in the buck-regulator output voltage

For this example, the specified transient load response is a 3% change in V_O for a load step from 0.01 A to 0.8 A. For this example, ΔI_O = 0.8 – 0.01 = 0.79 A and ΔV_O = 0.03 × 5 = 0.15 V. Using these numbers results in a minimum capacitance of 5.27 µF. This value does not consider the ESR of the output capacitor in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that must be take into consideration.

The catch diode of the regulator cannot sink current. Therefore any stored energy in the inductor produces an output-voltage overshoot when the load current rapidly decreases. Also, size the output capacitor to absorb the energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that is stored in the output capacitor increases the voltage on the capacitor. Size the capacitor to maintain the desired output voltage during these transient periods.

Use Equation 27 to calculate the minimum capacitance to keep the output voltage overshoot to a desired value.

Equation 27.

where

• L_O is the output inductance of the buck regulator
• I_OH is the output current of the buck regulator under heavy load
• I_OL is the output current of the buck regulator under light load
• V_f is the final peak output voltage of the buck regulator
• V_i is the initial capacitor voltage of the buck regulator

For this example, the worst-case load step is from 3.2 A to 0.01 A. The output voltage increases during this load transition, and the stated maximum in the specification is 3% of the output voltage (see the Electrical Characteristics table). This makes V_f = 1.03 × 5 = 5.15. V_i is the initial capacitor voltage, which is the nominal output voltage of 5 V. Using these numbers in Equation 27 yields a minimum capacitance of 22 µF.

Equation 28 calculates the minimum output capacitance needed to meet the output ripple-voltage specification. Equation 28 yields 0.8 µF.

Equation 28.

where

• V_O-ripple is the maximum allowable output ripple voltage of the buck regulator
• I_L-ripple is the inductor ripple current of the buck regulator

Use Equation 29 to calculate the maximum ESR required for the output capacitor to meet the output voltage ripple specification. As a result of Equation 29, the ESR should be less than 80 mΩ.

Equation 29.

The most stringent criterion for the output capacitor is 22 µF of capacitance to keep the output voltage in regulation during a load transient.

Factor in additional capacitance deratings for aging, temperature, and DC bias which increase this minimum value. For this example, two 47-µF, 25-V ceramic capacitors are used (see C4 and C5 in Figure 17). Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. Specify an output capacitor that can support the inductor ripple current. Some capacitor data sheets specify the root-mean-square (RMS) value of the maximum ripple current.

Use Equation 30 to calculate the RMS ripple current that the output capacitor must support. For this application, Equation 30 yields 191 mA.

Equation 30.

8.2.1.2.4 Catch Diode Selection for the Buck Regulator

The TPS65320D-Q1 device requires an external catch diode between the SW pin and GND (see D1 in Figure 17). The selected diode must have a reverse voltage rating equal to or greater than V_Imax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a good choice for the catch diode because of low forward voltage of these diodes. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage is. Although the design example has an input voltage up to 36 V, select a diode with a minimum of 40-V reverse voltage to allow input voltage transients up to the rated voltage of the TPS65320D-Q1 device.

For the example design, the selection of a Schottky diode is SL44-E3/57 based on the low forward voltage of this diode. This diode is also available in a larger package size, which has better thermal characteristics. The typical forward voltage of the SL44-E3/57 is 0.44 V.

Also, select a diode with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time, multiplied by the forward voltage of the diode, equals the conduction losses of the diode. At higher switching frequencies, consider the AC losses of the diode. The AC losses of the diode are because the charging and discharging of the junction capacitance and reverse recovery.

8.2.1.2.5 Input Capacitor Selection for the Buck Regulator

The TPS65320D-Q1 device requires a high-quality ceramic input decoupling capacitor (type X5R or X7R) of at least 3 µF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the TPS65320D-Q1 device. Use Equation 31 to calculate the input ripple current (I_CI(RMS)).

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. Minimize the capacitance variations because of temperature by selecting a dielectric material that is stable over temperature. Designers usually select X5R and X7R ceramic dielectrics for power regulator capacitors because these capacitors have a high capacitance-to-volume ratio and are fairly stable over temperature. Also, select the output capacitor with the DC bias taken into consideration. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases.

This design requires a capacitor with at least a 40-V voltage rating to support the maximum input voltage. Common standard capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, 63V, or 100 V. For this design example. The selection for this example is a 100-µF, 63-V bulk capacitance in parallel with a 2.2-µF ceramic capacitor (see C8 and C10 in Figure 17).

Equation 31.

The input-capacitance value determines the input ripple voltage of the regulator. Use Equation 32 to calculate the input ripple voltage (ΔV_I).

Equation 32.

Using the design example values, I_Omax = 3.2 A, C_I = 100 µF, ƒ_S = 2000 kHz, yields an input ripple voltage of 4 mV and an RMS input ripple current of 1.59 A.

8.2.1.2.6 Soft-Start Capacitor Selection for the Buck Regulator

The soft-start capacitor determines the minimum amount of time required for the output voltage to reach the nominal programmed value during power up which is useful if a load requires a controlled-voltage slew rate. This feature is also useful if the output capacitance is large and requires large amounts of current to charge the capacitor quickly to the output voltage level. The large currents required to charge the capacitor may make the TPS65320D-Q1 device reach the current limit, or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage-slew rate solves both of these problems.

The soft-start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Use Equation 33 to calculate the minimum soft-start time, t_ss, required to charge the output capacitor, C_O, from 10% to 90% of the output voltage, V_O, with an average load current of I_o(avg).

Equation 33.

In the example, to charge the effective output capacitance of 94 µF up to 5 V while allowing the average output current to be 3.2 A requires a 0.118 ms soft-start time.

When the soft-start time is known, use Equation 2 to calculate the soft-start capacitor. For the example circuit, the soft-start time is not too critical because the output-capacitor value is 2 × 47 µF, which does not require much current to charge to 5 V. The example circuit has the soft-start time set to an arbitrary value of 1 ms, which requires a 3.125-nF soft-start capacitor. This design uses the next-larger standard value of 3.3 nF.

8.2.1.2.7 Bootstrap Capacitor Selection for the Buck Regulator

Connect a 0.1-µF ceramic capacitor between the BOOT and SW pins for proper operation. TI recommends using a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or higher voltage rating.

8.2.1.2.8 Output Voltage and Feedback Resistor Selection for the Buck Regulator

The voltage divider of R1 and R2 sets the output voltage. For the design example, the selected value of R2 is 18.2 kΩ, and the calculated value of R1 is 95.3 kΩ. Because of current leakage of the FB1 pin, the current flowing through the feedback network should be greater than 1 μA to maintain the output-voltage accuracy. Selecting higher resistor values decreases the quiescent current and improves efficiency at low output currents, but can introduce noise immunity problems.

8.2.1.2.9 Frequency Compensation Selection for the Buck Regulator

Several possible methods exist to design closed loop compensation for DC-DC converters. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the buck regulator. Ignoring the slope compensation usually causes the actual crossover frequency to be lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero, and that the ESR zero is at least 10 times greater than the modulator pole.

To begin, use Equation 34 to calculate the modulator pole, ƒ_{P_mod}, and Equation 35 to calculate the ESR zero, ƒ_{z_mod}.

Equation 34.

Equation 35.

Use Equation 36 and Equation 37 to calculate an estimate starting point for the crossover frequency, ƒ_CO, to design the compensation.

Equation 36.

Equation 37.

For the example design, ƒ_{P_mod} is 1.08 kHz and ƒ_{Z_mod} is 564 kHz assuming an ESR of 3 mΩ. Equation 36 is the geometric mean of the modulator pole and the ESR zero and Equation 37 is the mean of the modulator pole and the switching frequency. Equation 36 yields 24.7 kHz and Equation 37 results 32.9 kHz. Use the lower value of Equation 36 or Equation 37 for an initial crossover frequency.

For this example, the target ƒ_CO value is 24.7 kHz. Next, calculate the compensation components. Use a resistor in series with a capacitor to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

The total loop gain, which consists of the product of the modulator gain, the feedback voltage-divider gain, and the error amplifier gain at ƒ_CO equal to 1. Use Equation 38 to calculate the compensation resistor, R3 (see the schematic in Figure 17).

Equation 38.

Assume the power-stage transconductance, gm_ps, is 10.5 S. The output voltage (V_O), reference voltage (V_ref), and amplifier transconductance, (gm_ea) are 5 V, 0.8 V, and 310 μS, respectively. The calculated value for R3 is 28.01 kΩ. For this design, use a value of 28 kΩ for R3. Use Equation 39 to set the compensation zero to the modulator pole frequency.

Equation 39.

Equation 37 yields 5.3 nF for compensating capacitor C1 (see the schematic in Figure 17). For this design, select a value of 5.6 nF for C1.

To implement a compensation pole as needed, use an additional capacitor, C2, in parallel with the series combination of R3 and C1. Use Equation 40 and Equation 41 to calculate the value of C2 and select the larger resulting value to set the compensation pole. Type 2B compensation does not use C2 because it would demand a low ESR of the output capacitor.

Equation 40.

Equation 41.

8.2.1.2.10 LDO Regulator

Depending on the end application, use different values of external components can be used. To program the output voltage, carefully select the feedback resistors, R5 and R6 (see the schematic in Figure 17). Using smaller resistors results in higher current consumption, whereas using very large resistors impacts the sensitivity of the regulator. Therefore selecting feedback resistors such that the sum of R5 and R6 is between 20 kΩ and 200 kΩ is recommended.

If the desired regulated output voltage is 3.3 V on selecting R6, the value of R5 can be calculated. With V_ref = 0.8 V (typical), V_O = 3.3 V, and selecting R6 = 30.1 kΩ, the calculated value of R5 is 95.3 kΩ.

An output capacitor for the LDO regulator is required (see C10 in Figure 17) to prevent the output from temporarily dropping down during fast load steps. TI recommends a low-ESR ceramic capacitor with dielectric of type X5R or X7R. Additionally, a bypass capacitor can be connected at the output to decouple high-frequency noise based on the requirements of the end application.

8.2.1.2.11 Power Dissipation

1. Conduction loss:
Equation 42. P_CON = I_O² × r_DS(on) × (V_O / V_I)
where
• I_O is the buck regulator output current
• V_O is the buck regulator output voltage
• V_I is the input voltage
2. Switching loss:
Equation 43. P_SW = ½ × V_I × I_O × (t_r + t_f) × f_S
where
• t_r is the FET switching rise time (t_r maximum = 20 ns)
• t_f is the FET switching fall time (t_f maximum = 20 ns)
• ƒ_S is the switching frequency of the buck regulator
3. Gate drive loss:
Equation 44. P_Gate = V_drive × Q_g × ƒ_sw
where
• V_drive is the FET gate-drive voltage (typically V_drive = 6 V)
• Q_g = 1 × 10^–9 (nC, typical)

8.2.1.2.12 Power Dissipation Losses of the LDO Regulator

8.2.1.2.13 Total Device Power Dissipation Losses and Junction Temperature

1. Supply loss:
Equation 46. P_IC = V_I × I_Q-normal
2. Total power loss:
Equation 47. P_Total = P_CON + P_SW + P_Gate + P_LDO + P_IC

For a given operating ambient temperature T_A:

For a given maximum junction temperature T_J-max = 150°C, the allowed Total power dissipation is given as:

Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the Schottky diode, and trace resistance that impact the overall efficiency of the regulator.

Figure 18 shows the thermal derating profile of the 14-pin HTSSOP Package With PowerPAD™ . It is important to consider additional cooling strategies if necessary to maintain the junction temperature of the device below the maximum junction temperature of 150 °C.

Figure 18. Thermal Derating Profile ofTPS65320D-Q1 in 14-pin HTSSOP Package With PowerPAD