ZHCSCO8E June 2014 – May 2019 TPS65283 , TPS65283-1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 典型電路原理圖
- 5 修訂歷史記錄
- 6 說明 （續）
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Power Switch Detailed Description
- 9.3.2
Buck DC-DC Converter Detailed Description
- 9.3.2.1 Output Voltage
- 9.3.2.2 Adjustable Switching Frequency
- 9.3.2.3 Synchronization
- 9.3.2.4 Error Amplifier
- 9.3.2.5 Slope Compensation
- 9.3.2.6 Enable and Adjusting UVLO
- 9.3.2.7 Internal V7V Regulator
- 9.3.2.8 Short Circuit Protection
- 9.3.2.9 Bootstrap Voltage (BST) and Low Dropout Operation
- 9.3.2.10 Output Overvoltage Protection (OVP)
- 9.3.2.11 Power Good
- 9.3.2.12 Power-Up Sequencing
- 9.3.2.13 Thermal Performance
- 9.4 Device Functional Modes
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
- RGE|24
散熱焊盤機械數據 (封裝 | 引腳)
- RGE|24
訂購信息
9.3.2.3 Synchronization
The user can implement an internal phase locked loop (PLL) to allow synchronization between 200 kHz to 2 MHz, and to easily switch from resistor mode to synchronization mode. To implement the synchronization feature, connect a square wave clock signal to the ROSC pin with a duty cycle between 20% and 80%. The clock signal amplitude must transition lower than 0.4 V and higher than 2 V. The start of the switching cycle is synchronized to the falling edge of ROSC pin.
In applications where both resistor mode and synchronization mode are needed, configure the device as shown in Figure 26. Before the external clock is present, the device works in resistor mode and the switching frequency is set by ROSC resistor. When the external clock is present, the synchronization mode overrides the resistor mode.
