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ZHCSCO8E June 2014 – May 2019 TPS65283 , TPS65283-1

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- MPQF124G

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- QFND008AA

訂購信息

8.5 Electrical Characteristics

T_J = 25°C, V_IN1 = V_IN2 = 12 V, ƒ_SW = 500 kHz, R_PG1 = R_PG2 = R_nFAULTx = 100 kΩ, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY
V_IN	Input voltage range		4.5		18	V
IDD_SDN	Shutdown supply current	V_{SW_EN} = V_EN1 = V_EN2 = 0		5.5	10	µA
IDD_{Q_NSW}	None switching quiescent current	EN1 = EN2 = high, V_FB1 = V_FB2 = 1 V, With buck1 and buck2 not switching		0.5		mA
UVLO	Input voltage undervoltage lockout (UVLO)	V_IN1 rising	4	4.25	4.5	V
		V_IN1 falling	3.5	3.75	4	V
		Hysteresis		500		mV
V_7V	Internal biasing supply	V_V7V load current = 0 A, V_IN1 = 12 V	6.05	6.3	6.49	V
I_{OCP_V7V}	Current limit of V7V LDO			180		mA
OSCILLATOR
ƒ_SW	Switching frequency	ROSC = 100 kΩ	400	500	600	kHz
T_{SYNC_w}	Clock sync minimum pulse width		80			ns
V_{SYNC_HI}	Clock sync high threshold				2	V
V_{SYNC_LO}	Clock sync low threshold		0.4			V
V_{SYNC_D}	Clock falling edge to LX rising edge delay				120	ns
F_SYNC	Clock sync frequency range		200		2000	kHz
BUCK1/BUCK2 CONVERTER
V_FB	Feedback voltage	V_COMP1 = V_COMP2 = 1.2 V, T_J = 25°C	0.594	0.6	0.606	V
V_FB	Feedback voltage	V_COMP1 = V_COMP2= 1.2 V, T_J = –40°C to 125°C	0.588	0.6	0.612	V
G_{m_EA}	Error amplifier transconductance	–2 µA < ICOMPX < 2 µA		300		µS
G_{m_SRC}	COMP1/COMP2 voltage to inductor current Gm⁽¹⁾	I_LX1 = I_LX2 = 0.5 A		7.4		A/V
V_ENXH	EN1, EN2 high level input voltage			1.2	1.26	V
V_ENXL	EN1, EN2 low-level input voltage		1.1	1.15		V
I_ENX	EN1, EN2 pullup current	V_EN1 = V_EN2 = 1 V		3.6		µA
I_ENX	EN1, EN2 pullup current	V_EN1 = V_EN2 = 1.5 V		6.6		µA
I_ENhys	I_EN1 / I_EN2 hysteresis current			3		µA
T_{ON_MIN}	Minimum on time	T_J = 25°C		80	100	ns
T_{ON_MIN}	Minimum on time	T_J = –40°C to 125°C			120	ns
T_{SS_INT}	Internal soft-start time			2.4		ms
I_LIMIT1	Buck1 peak inductor current limit		4.25	5	5.75	A
I_LIMITS1	Buck1 low-side sink current limit			1.7		A
I_LIMIT2	Buck2 peak inductor current limit		3.2	3.75	4.3	A
I_LIMITS2	Buck2 low side sink current limit			1.3		A
Rdson1_HS	High-side FET on-resistance in Buck1	V7V = 6.25 V		100		mΩ
Rdson1_LS	Low-side FET on-resistance in buck1	V7V = 6.25 V		65		mΩ
Rdson2_HS	High-side FET on-resistance in Buck2	V7V = 6.25 V		140		mΩ
Rdson2_LS	Low-side FET on-resistance in buck2	V7V = 6.25 V		95		mΩ
T_{HICCUP_WAIT}	Hiccup wait time			4		ms
T_{HICCUP_RE}	Hiccup time before restart			64		ms
POWER GOOD
V_{th_PG}	Feedback voltage threshold	V_FB1 / V_FB2 UV falling		92.5%
		V_FB1 / V_FB2 UV rising		95%
		V_FB1 / V_FB2 OV rising		107.5%
		V_FB1 / V_FB2 OV falling		105%
T_{DEGLITCH(PGF)}	PG1/PG2 deglitch time (falling edge)			1		ms
T_{DEGLITCH(PGR)}	PG1/PG2 deglitch time (rising edge)			2		ms
I_PG	Power Good pin leakage	V_FB1 = V_FB2 = 0.6 V			1	µA
V_{LOW_PG}	PG1/PG2 pin low voltage	Force FB₁ = FB₂ = 0.5 V, sink 1 mA to PG1/PG2 pin			0.4	V
POWER DISTRIBUTION SWITCH
V_SWIN	Power switch input voltage range		2.4		6	V
IDD_QH	Supply current, device enabled	No load on SW_OUT, RSET = 20 kΩ		140		µA
V_{UVLO_SW}	Power switch input undervoltage lockout	V_SWIN rising	2.15	2.25	2.35	V
		V_SWIN falling	2.05	2.15	2.25	V
		Hysteresis		100		mV
R_{DSON_SW}	Power switch NMOS on-resistance	RGE package, V_SWIN = 5 V, I_OUT= 0.5 A, T_J= 25°C, including bond wire resistance		60		mΩ
R_{DSON_SW}	Power switch NMOS on-resistance	RGE package, V_SWIN = 2.5 V, I_OUT= 0.5 A, T_J= 25°C, including bond wire resistance		60		mΩ
t_{D_on}	Turn-on delay time	V_SWIN = 5 V, C_L= 10 µF, R_L= 100 Ω		1.1		ms
t_{D_off}	Turn-off delay time	(See Figure 1)		1.2		ms
t_r	Output rise time			0.65		ms
t_f	Output fall time			1.54		ms
I_OS	Current limit threshold (maximum DC current delivered to load) and short circuit current, OUT connect to ground	R_SET = 14.3 kΩ	1.575	1.75	1.925	A
		R_SET = 20 kΩ	1.125	1.25	1.375
		R_SET = 50 kΩ	0.4	0.5	0.6
		R_SET = 80.6 kΩ, T_J = 0°C to 90°C	0.15	0.325	0.5
T_{DEGLITCH(OCP)}	Switch overcurrent fault deglitch	Fault assertion or deassertion due to overcurrent condition	6	8	10
T_{DEGLITCH(OCP)}	Switch overcurrent fault deglitch	Fault assertion or deassertion due to overcurrent condition	6	8	10	ms
V_{L_nFAULT}	nFAULT pin output low voltage	I_nFAULT = 1 mA		150	300	mV
V_ENSWH	SW_EN high-level input voltage		2			V
V_ENSWL	SW_EN low-level input voltage				0.4	V
R_DIS	Discharge resistance⁽²⁾	V_{SW_IN} = 5 V, V_{SW_EN} = 0 V		100		Ω
THERMAL SHUTDOWN
T_{TRIP_BUCK}	Thermal protection trip point	Temperature rising		160		°C
T_{HYST_BUCK}	Thermal protection trip point	Hysteresis		20		°C
T_{TRIP_SW}	Power switch thermal protection trip point Power switch in overcurrent condition	Temperature rise		145		°C
T_{HYST_SW}		Hysteresis		20		°C

(1) Specified by design.

(2) The discharge function is active when the device is disabled (when enable is deasserted). The discharge function offers a resistive discharge path for the external storage capacitor.

TPS65283 TPS65283-1 power_switches_test_circuit_voltage_waveforms_slvscl3.gif

Figure 1. Power Switches Test Circuit and Voltage Waveforms

TPS65283 TPS65283-1 response_time_short_circuit_waveform_slvscl3.gif

Figure 2. Response Time to Short Circuit Waveform

TPS65283 TPS65283-1 output_voltage_vs_current_limit_threshold_slvscl3.gif

Figure 3. Output Voltage vs Current Limit Threshold