ZHCSIX2 October 2018 TPS65216
PRODUCTION DATA.
- 1器件概述
- 2Pin Configuration and Functions
- 3Specifications
-
4Detailed Description
- 4.1 Overview
- 4.2 Functional Block Diagram
- 4.3
Feature Description
- 4.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 4.3.1.1 Power-Up Sequencing
- 4.3.1.2 Power-Down Sequencing
- 4.3.1.3 Strobes 1 and 2
- 4.3.1.4 Supply Voltage Supervisor and Power Good (PGOOD)
- 4.3.1.5 Internal LDO (INT_LDO)
- 4.3.1.6 Current Limited Load Switch
- 4.3.1.7 LDO1
- 4.3.1.8 UVLO
- 4.3.1.9 Power-Fail Comparator
- 4.3.1.10 DCDC3 / DCDC4 Power-Up Default Selection
- 4.3.1.11 I/O Configuration
- 4.3.1.12 Push Button Input (PB)
- 4.3.1.13 AC_DET Input (AC_DET)
- 4.3.1.14 Interrupt Pin (INT)
- 4.3.1.15 I2C Bus Operation
- 4.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 4.4 Device Functional Modes
- 4.5
Register Maps
- 4.5.1 Password Protection
- 4.5.2 FLAG Register
- 4.5.3
TPS65216Registers
- 4.5.3.1 CHIPID Register (subaddress = 0x0) [reset = 0x5]
- 4.5.3.2 INT1 Register (subaddress = 0x1) [reset = 0x0]
- 4.5.3.3 INT2 Register (subaddress = 0x2) [reset = 0x0]
- 4.5.3.4 INT_MASK1 Register (subaddress = 0x3) [reset = 0x0]
- 4.5.3.5 INT_MASK2 Register (subaddress = 0x4) [reset = 0x0]
- 4.5.3.6 STATUS Register (subaddress = 0x5) [reset = 00XXXXXXb]
- 4.5.3.7 CONTROL Register (subaddress = 0x6) [reset = 0x0]
- 4.5.3.8 FLAG Register (subaddress = 0x7) [reset = 0x0]
- 4.5.3.9 PASSWORD Register (subaddress = 0x10) [reset = 0x0]
- 4.5.3.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x0]
- 4.5.3.11 ENABLE2 Register (subaddress = 0x12) [reset = 0x0]
- 4.5.3.12 CONFIG1 Register (subaddress = 0x13) [reset = 0x4C]
- 4.5.3.13 CONFIG2 Register (subaddress = 0x14) [reset = 0xC0]
- 4.5.3.14 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
- 4.5.3.15 DCDC1 Register (offset = 0x16) [reset = 0x99]
- 4.5.3.16 DCDC2 Register (subaddress = 0x17) [reset = 0x99]
- 4.5.3.17 DCDC3 Register (subaddress = 0x18) [reset = 0x8C]
- 4.5.3.18 DCDC4 Register (subaddress = 0x19) [reset = 0xB2]
- 4.5.3.19 SLEW Register (subaddress = 0x1A) [reset = 0x6]
- 4.5.3.20 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
- 4.5.3.21 SEQ1 Register (subaddress = 0x20) [reset = 0x0]
- 4.5.3.22 SEQ2 Register (subaddress = 0x21) [reset = 0x0]
- 4.5.3.23 SEQ3 Register (subaddress = 0x22) [reset = 0x98]
- 4.5.3.24 SEQ4 Register (subaddress = 0x23) [reset = 0x75]
- 4.5.3.25 SEQ5 Register (subaddress = 0x24) [reset = 0x12]
- 4.5.3.26 SEQ6 Register (subaddress = 0x25) [reset = 0x63]
- 4.5.3.27 SEQ7 Register (subaddress = 0x26) [reset = 0x3]
- 5Application and Implementation
- 6Power Supply Recommendations
- 7Layout
- 8器件和文檔支持
- 9機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSL|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSL|48
訂購信息
4.3.1.13 AC_DET Input (AC_DET)
The AC_DET pin is a CMOS-type input used in three different ways to control the power-up of the PMIC:
- In a battery operated system, AC_DET is typically connected to an external battery charger with an open-drain power-good output pulled low when a valid charger supply is connected to the system. A falling edge on the AC_DET pin causes the PMIC to power up.
- In a non-portable system, the AC_DET pin may be shorted to ground and the IC powers up whenever system power is applied to the chip.
- If none of the above behaviors are desired, AC_DET may be tied to system power (IN_BIAS). Power-up is then controlled through the push-button input or PWR_EN input.
A. Portable Systems
B. Non-portable Systems
C. Disabled
Figure 4-17 AC_DET Pin Configurations 
Figure 4-18 AC_DET Input Deglitch and Power-Up Timing (Portable Systems) In ACTIVE state, the TPS65216 monitors the AC_DET input and issues an interrupt when the pin status changes, such as when it drops below or rises above the AC_DET input-low or input-high thresholds. The interrupt is masked by the ACM bit in the INT_MASK1 register.
Figure 4-19 AC_STATE Pin NOTE
Interrupts are issued whenever the AC_DET pin status changes. The AC_STATE bit reflects the current status of the AC_DET input.