ZHCS259B July 2011 – August 2015 TPS65142
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 AVDD Boost Regulator
- 7.3.2 Regulated Positive Charge Pump
- 7.3.3 Negative Charge Pump
- 7.3.4 Gate Voltage Shaping
- 7.3.5 VCOM Buffer
- 7.3.6 Reset
- 7.3.7 Under-voltage Lockout (UVLO)
- 7.3.8 Thermal Shutdown
- 7.3.9 WLED Boost Regulator
- 7.3.10 Current Sinks
- 7.3.11 Unused IFB Pins
- 7.3.12 PWM Dimming
- 7.3.13 Enabling the WLED Driver
- 7.3.14 Soft-Start of WLED Boost Regulator
- 7.3.15 Protection of WLED Driver
- 7.3.16 Power Up/Down Sequence
- 8 Application and Implementation
- 9 器件和文檔支持
- 10機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTG|32
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTG|32
訂購信息
6 Specifications
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.1 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process..
6.2 Recommended Operating Conditions
| MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|
| VIN | Input voltage range | 2.3 | 6 | V | |
| VS | AVDD Boost output voltage range(1) | 16.5 | V | ||
| VGH | Positive charge pump output voltage range | 32 | V | ||
| VBAT | Battery voltage range | 4.5 | 24 | V | |
| VO | WLED boost converter output voltage | 38 | V | ||
| VGL | Negative charge pump output voltage range | –14 | V | ||
| L1 | Inductor for the AVDD boost converter(2) | 4.7 | 10 | µH | |
| L2 | Inductor for the WLED boost converter | 4.7 | 10 | µH | |
| CIN | Input decoupling capacitor | 1 | µF | ||
| CO1 | Output decoupling capacitor of the AVDD boost converter | 20 | µF | ||
| CO2 | Output decoupling capacitor of the WLED boost converter | 2.2 | 10 | µF | |
| TA | Operating ambient temperature | –40 | 85 | °C | |
| TJ | Operating junction temperature | –40 | 125 | °C |
(1) Maximum output voltage is limited by the overvoltage protection and not the maximum power switch rating
(2) Refer to application section for further information.
6.3 Thermal Information
| THERMAL METRIC(1) | WQFN | UNITS | |
|---|---|---|---|
| RTG (32 PINS) | |||
| RθJA | Junction-to-ambient thermal resistance | 35.4 | °C/W |
| RθJCtop | Junction-to-case (top) thermal resistance | 19.9 | |
| RθJB | Junction-to-board thermal resistance | 5.6 | |
| ψJT | Junction-to-top characterization parameter | 0.2 | |
| ψJB | Junction-to-board characterization parameter | 5.4 | |
| RθJCbot | Junction-to-case (bottom) thermal resistance | 1.7 | |
(1) 有關(guān)傳統(tǒng)和新熱指標(biāo)的更多信息，請(qǐng)參見《半導(dǎo)體和 IC 封裝熱指標(biāo)》應(yīng)用報(bào)告，SPRA953。
6.4 Electrical Characteristics
VIN = 3.3 V, VS = 9V, VGH = 20 V, VBAT = 10.8V, IISET = 15µA, VIFBx = 0.5V, EN = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY | ||||||
| IQ(IN) | Operating quiescent current into VIN | Device not switching | 0.17 | 0.5 | mA | |
| IQ(VGH) | Operating quiescent current into VGH | VGH = 20 V, VFLK not oscillating | 22 | 40 | µA | |
| IQ(SUP) | Operating quiescent current into SUP | Device not switching. VS = 9 V, EN = high | 2.8 | mA | ||
| Device not switching. VS = 9 V, EN = GND | 2.5 | |||||
| ISD(VIN) | Shutdown current into VIN | VIN = 1.8 V, VS = GND | 20 | 33 | µA | |
| ISD(VGH) | Shutdown current into VGH | VIN = 1.8 V, VGH = 32 V | 30 | 50 | µA | |
| ISD(SUP) | Shutdown current into SUP | VIN = 1.8 V, VS = 16.5 V | 3 | 5 | µA | |
| IQ(BAT) | VBAT pin quiescent current | WLED boost regulator switching, no load | 0.2 | mA | ||
| ISD(BAT) | VBAT pin shutdown current | EN = GND | 18 | µA | ||
| IQ(VO) | VO pin quiescent current | VO = 35 V | 75 | µA | ||
| UVLO | VIN under voltage lockout threshold | VIN falling | 1.9 | 2.1 | V | |
| VIN rising | 2.2 | |||||
| VBAT under voltage lockout threshold | VBAT rising | 4.45 | V | |||
| VBAT falling | 3.9 | |||||
| UVLO voltage of WLED control circuit | 2.2 | 2.5 | V | |||
| LOGIC SIGNALS FREQ, VFLK, EN, DCTRL | ||||||
| VIH | Logic high input voltage | VIN = 2.5 V to 6 V | 2 | V | ||
| VIL | Logic low input voltage | VIN = 2.5 V to 6 V | 0.5 | V | ||
| ILKG | Input leakage current of VFLK pin | VFLK = 6 V, FREQ = GND | 0.1 | µA | ||
| RPD | Pull-down resistance for EN and DCTRL pins | EN = DCTRL = 3.3 V | 400 | 800 | 1600 | kΩ |
| AVDD BOOST CONVERTER | ||||||
| VS | Output voltage boost(1) | 7 | 16.5 | V | ||
| VOVP | Overvoltage protection | VS rising | 16.9 | 18 | 19 | V |
| VFB | Feedback regulation voltage | TA = –40°C to 85°C | 1.226 | 1.24 | 1.254 | V |
| TA = 25°C | 1.23 | 1.24 | 1.25 | |||
| IFB | Feedback input bias current | VFB = 1.240 V | 0.1 | µA | ||
| rDS(ON) | N-channel MOSFET on-resistance | VIN = VGS = 5 V, ISW = current limit | 0.13 | 0.38 | Ω | |
| VIN = VGS = 3.3 V, ISW = current limit | 0.15 | 0.44 | ||||
| ILkg(SW) | AVDD Boost converter SW leakage current | VIN = 1.8 V, VSW = 17 V, Device not switching | 30 | µA | ||
| ILIM | N-Channel MOSFET current limit | VIN = 2.5 V to 6 V | 1.8 | 2.5 | 3.2 | A |
| VIN = 2.3 V to 2.5 V | 1.5 | A | ||||
| fBOOST | Switching frequency | FREQ = high | 0.9 | 1.2 | 1.5 | MHz |
| FREQ = low | 470 | 625 | 780 | kHz | ||
| TSS | Softstart time | FREQ = high, L1 = 6.8 µH, CO1 = 2 0µF and 10 mA load current |
2 | ms | ||
| Line regulation | VIN = 2.5 V … 6 V, IOUT = 10 mA | 0.008 | %/V | |||
| Load regulation | IOUT = 0 mA …500 mA | 0.15 | %/A | |||
| VGH REGULATOR | ||||||
| fSWP | Switching frequency | 0.5 x fBOOST | MHz | |||
| VFBP | Reference voltage of feedback | TA = –40°C to 85°C | 1.210 | 1.240 | 1.270 | V |
| TA = 25°C | 1.221 | 1.240 | 1.259 | |||
| IFBP | Feedback input bias current | VFBP = 1.240 V | 0.1 | µA | ||
| rDS(ON)P1 | DRVP RDS(ON) (PMOS) | VS = 9 V, I(DRVP) = 40 mA | 8 | 20 | Ω | |
| rDS(ON)N1 | DRVP RDS(ON) (NMOS) | VS = 9 V, I(DRVP) = –40 mA | 3 | 10 | Ω | |
| VGL REGULATOR | ||||||
| fSWN | Switching frequency | 0.5 x fBOOST | MHz | |||
| VREF | Reference voltage | 3.05 | 3.12 | 3.18 | V | |
| VFBN | Reference voltage of feedback | –48 | 0 | 48 | mV | |
| IFBN | Feedback input bias current | VFBN = 0 V | 0.1 | µA | ||
| rDS(ON)P2 | DRVN RDS(ON) (PMOS) | VS = 9 V, I(DRVN) = 40 mA | 8 | 20 | Ω | |
| rDS(ON)N2 | DRVN RDS(ON) (NMOS) | VS = 9 V, I(DRVN) = –40 mA | 3 | 10 | Ω | |
| GATE VOLTAGE SHAPING VGHM | ||||||
| I(DPM) | Capacitor charge current VDPM pin | 17 | 20 | 23 | µA | |
| rDS(ON)M1 | VGH to VGHM rDS(ON) (M1 PMOS) | VFLK = low, I(VGHM) = 20 mA | 13 | 25 | Ω | |
| rDS(ON)M2 | VGHM to RE rDS(ON) (M2 PMOS) | VFLK = high, I(VGHM) = 20 mA, VGHM = 7.5 V | 13 | 25 | Ω | |
| RESET | ||||||
| VIN(DET) | VIN voltage range for reset detection | 1.6 | 6 | V | ||
| V(DET) | Reset IC threshold | Falling | 1.074 | 1.1 | 1.126 | V |
| V(DET_HYS) | Reset IC threshold hysteresis | 65 | mV | |||
| I(DET_B) | Reset IC input bias current | V(DET) = 1.1 V | 0.1 | µA | ||
| IXAO | Reset sink current capability(2) | V(XAO_ON) = 0.5 V | 1 | mA | ||
| ILKG(XAO) | Reset leakage current | V(XAO) = VIN = 3.3 V | 2 | µA | ||
| VCOM BUFFER | ||||||
| VSUP | SUP input supply range(3) | 7 | 16.5 | V | ||
| IB | Input bias current | VCM = V(OPI) = VSUP/2 = 4.5 V | –1 | 1 | µA | |
| VCM | Common Mode Input Voltage Range | VOFFSET = 10 mV, I(OPO) = 10 mA | 2 | VS – 2 | V | |
| CMRR | Common Mode Rejection Ratio(4) | VCM = V(OPI) = V(SUP)/2 = 4.5 V, 1 MHz | 66 | dB | ||
| AVOL | Open Loop Gain(4) | VCM = V(OPI) = V(SUP)/2 = 4.5 V, no load | 90 | dB | ||
| VOL | Output Voltage Swing Low | I(OPO) = 10 mA | 0.10 | 0.25 | V | |
| VOH | Output Voltage Swing High | I(OPO) = 10 mA | VS – 0.8 | VS – 0.65 | V | |
| ISC | Short Circuit Current | Source (V(OPI) = 4.5V, V(OPO) = GND) | 150 | mA | ||
| Sink (V(OPI) = 4.5 V, V(OPO) = 9 V) | 150 | |||||
| IO | Output Current | Source (V(OPI) = 4.5 V, V(OFFSET) = 15 mV) | 150 | mA | ||
| Sink (V(OPI) = 4.5 V, V(OFFSET) = 15 mV) | 140 | |||||
| PSRR | Power Supply Rejection Ratio(4) | 40 | dB | |||
| SR | Slew Rate(4) | AV = 1, V(OPI) = 2 VPP | 40 | V/µs | ||
| BW | –3 dB Bandwidth(4) | AV = 1, V(OPI) = 60 mVPP | 50 | MHz | ||
| WLED CURRENT REGULATION | ||||||
| V(ISET) | ISET pin voltage | 1.204 | 1.229 | 1.253 | V | |
| K(ISET) | Current multiple IOUT/ISET (5) | ISET current = 20 µA | 1000 | |||
| IFB | Current accuracy (5) | ISET current = 20 µA | 19.4 | 20 | 20.6 | mA |
| Km | (Imax–Imin)/IAVG | ISET current = 20 µA | 1% | 2.5% | ||
| ILKG | IFB pin leakage current | IFB voltage = 20 V on all pins | 3 | µA | ||
| I(IFB_MAX) | Current sink max output current | IFB = 500 mV | 28 | mA | ||
| WLED BOOST OUTPUT REGULATION | ||||||
| V(IFB_L) | VO dial up threshold | Measured on V(IFB) min | 400 | mV | ||
| V(IFB_H) | VO dial down threshold | Measured on V(IFB) min | 700 | mV | ||
| V(reg_L) | Minimum VO regulation voltage | 16 | V | |||
| VO(step) | VO stepping voltage | 100 | 150 | mV | ||
| WLED BOOST REGULATOR POWER SWITCH | ||||||
| R(PWM_SW) | PWM FET on-resistance | 0.2 | 0.45 | Ω | ||
| I(LN_NFET) | PWM FET leakage current | V(BL_SW) = 35 V, TA = 25°C | 1 | µA | ||
| WLED OSCILLATOR | ||||||
| fS | Oscillator frequency | 0.9 | 1.0 | 1.2 | MHz | |
| Dmax | Maximum duty cycle of WLED Boost | IFB = 0 V | 89% | 94% | ||
| Dmin | Minimum duty cycle of WLED Boost | 7% | ||||
| CURRENT LIMIT, OVER VOLTAGE AND SHORT CIRCUIT PROTECTIONS | ||||||
| ILIM | N-Channel MOSFET current limit | D = DMAX | 1.5 | 3 | A | |
| VOVP | VO overvoltage threshold | Measured on the VO pin | 38 | 39 | 40 | V |
| VOVP(IFB) | IFB overvoltage threshold | Measured on the IFBx pin | 15 | 17 | 20 | V |
| VSC | Short circuit detection threshold | VBAT –VO, VO ramp down | 1.7 | 2.5 | V | |
| VSC(dly) | Short circuit detection delay during start up | 32 | ms | |||
| THERMAL SHUTDOWN | ||||||
| TSD | Thermal shutdown | Temperature rising | 150 | °C | ||
| TSDHYS | Thermal shutdown hysteresis | 14 | °C | |||
(1) Maximum output voltage limited by the overvoltage protection and not the maximum power switch rating
(2) External pull-up resistor to be chosen so that the current flowing into XAO Pin (/XAO = 0 V) when active is below I(XAO) MIN = 1 mA.
(3) Maximum output voltage limited by the Overvoltage Protection and not the maximum Power Switch rating.
(4) Typical values are for reference only
(5) Tested at TA = 25°C to 85°.
6.5 Timing Requirements
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| td | Rising edge delay between VBAT and VIN, measured at their respective rising edge UVLO threshold voltages (see Figure 32). (1) | 0 | s | ||
(1) This means that the voltage on the VBAT pin must exceed its UVLO threshold before the voltage on the VIN pin rises above its UVLO threshold.
6.6 Typical Characteristics
