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ZHCSCH4H June 2013 – November 2016 TPS65132

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RVC|20
- MPQF234A
YFF|15
- MXBG163C

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings^⁽¹⁾^⁽²⁾

over operating free-air temperature range (unless otherwise noted)

		VALUE		UNIT
		MIN	MAX	UNIT
Voltage range	CFLY1, EN, ENN, ENP, OUTP, REG, SCL, SDA, SW, SYNC, VIN	–0.3	7	V
Voltage range	CFLY2, OUTN	–7	0.3	V
Continuous total power dissipation		See Thermal Information
Operating junction temperature, T_J		–40	150	°C
Operating ambient temperature, T_A		–40	85	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to ground.

7.2 ESD Ratings

		VALUE		UNIT
V_ESD	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000		V
V_ESD	Charged device model (CDM) per JEDEC specification JESD22-C101, all pins⁽²⁾	±500		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

		MIN	MAX	UNIT
V_IN	Input voltage range	2.5	5.5	V
L	Inductor⁽¹⁾	2.2	4.7	µH
C_IN	Input capacitor⁽¹⁾⁽²⁾	4.7		µF
C_FLY	Flying capacitor⁽¹⁾⁽²⁾	2.2		µF
C_OUTP, C_OUTN, C_REG	Output capacitors⁽¹⁾⁽²⁾	4.7		µF
T_A	Operating ambient temperature	–40	85	°C
T_J	Operating junction temperature	–40	125	°C

(1) Please see Detailed Description section for further information.

(2) X7R (or better dielectric material) is recommended.

7.4 Thermal Information

THERMAL METRIC^⁽¹⁾		TPS65132	TPS65132	UNIT
		YFF	RVC
		(15) BALLS	(20) PINS
R_θJA	Junction-to-ambient thermal resistance	76.5	39.0	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	0.2	42.7	°C/W
R_θJB	Junction-to-board thermal resistance	44	13.6	°C/W
ψ_JT	Junction-to-top characterization parameter	1.6	0.6	°C/W
ψ_JB	Junction-to-board characterization parameter	43.4	13.6	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	N/A	3.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

V_IN = 3.7 V, EN = ENN = ENP = V_IN, V_POS = 5.4 V, V_NEG = –5.4 V, T_A = –40°C to 85°C; typical values are at T_A = 25°C
(unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
V_IN	Input voltage range		2.5		5.5	V
V_UVLO	Undervoltage lockout threshold	V_IN rising	2.3		2.5	V
V_UVLO	Undervoltage lockout threshold	V_IN falling	2.1		2.3	V
I_Q	Quiescent current			0.54		mA
	Thermal shutdown			140		°C
	Thermal shutdown hysteresis			5		°C
LOGIC EN, ENN, ENP, SYNC
V_IH	High level input voltage	V_IN = 2.5 V to 5.5 V	1.1			V
V_IL	Low level input voltage	V_IN = 2.5 V to 5.5 V			0.4	V
R_EN	Pulldown resistors			200		kΩ
LOGIC SCL, SDA
V_IH	High level input voltage	V_IN = 2.5 V to 5.5 V	1.1			V
V_IL	Low level input voltage	V_IN = 2.5 V to 5.5 V			0.54	V
BOOST CONVERTER
I_LIM	Boost converter valley current limit		0.9	1.2	1.5	A
f_SW	Boost converter switching frequency		1.35	1.80	2.25	MHz
LDO OUTPUT V_POS
V_POS	Positive output voltage range		4.0		6.0	V
V_{POS_acc}	Positive output voltage accuracy		–1 %		+1 %
I_POS	Positive output current capability		200			mA
V_DO	Dropout voltage	V_REG = V_POS(NOM) = 5.4V, I_OUT = 150 mA		160		mV
	Line regulation	V_IN = 2.5 V to 5.5 V, I_OUT = 40 mA		2.7		mV
	Load regulation	ΔI_OUT = 80 mA		3.4		%/A
R_D	Discharge resistor			70		Ω
NEGATIVE CHARGE PUMP OUTPUT V_NEG
V_NEG	Negative output voltage range		–6.0		–4.0	V
V_{NEG_acc}	Negative output voltage accuracy		–1 %		+1 %
I_NEG	Negative output current capability	40mA MODE	40			mA
I_NEG	Negative output current capability	80mA MODE	80			mA
I_NEG	Negative output current capability	TPS65132Sx, SYNC = HIGH	150			mA
f_OSC	Negative charge pump switching frequency		0.8	1.0	1.2	MHz
	Line regulation	V_IN = 2.5 V to 5.5 V, I_OUT = 40 mA		3.3		mV
	Load regulation	ΔI_OUT = 80 mA		6.1		%/A
R_D	Discharge resistor			20		Ω

7.6 I²C Interface Timing Requirements / Characteristics ^⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
f_SCL	SCL clock frequency	Standard mode		100	kHz
f_SCL	SCL clock frequency	Fast mode		400	kHz
t_LOW	LOW period of the SCL clock	Standard mode	4.7		µs
t_LOW	LOW period of the SCL clock	Fast mode	1.3		µs
t_HIGH	HIGH period of the SCL clock	Standard mode	4.0		µs
t_HIGH	HIGH period of the SCL clock	Fast mode	600		ns
t_BUF	Bus free time between a STOP and START condition	Standard mode	4.7		µs
t_BUF	Bus free time between a STOP and START condition	Fast mode	1.3		µs
t_hd;STA	Hold time for a repeated START condition	Standard mode	4.0		µs
t_hd;STA	Hold time for a repeated START condition	Fast mode	600		ns
t_su;STA	Setup time for a repeated START condition	Standard mode	4.7		µs
t_su;STA	Setup time for a repeated START condition	Fast mode	600		ns
t_su;DAT	Data setup time	Standard mode	250		ns
t_su;DAT	Data setup time	Fast mode	100		ns
t_hd;DAT	Data hold time	Standard mode	0.05	3.45	µs
t_hd;DAT	Data hold time	Fast mode	0.05	0.9	µs
t_RCL1	Rise time of SCL signal after a repeated START condition and after an acknowledge bit	Standard mode	20 + 0.1C_B	1000	ns
t_RCL1		Fast mode	20 + 0.1C_B	1000	ns
t_RCL	Rise time of SCL signal	Standard mode	20 + 0.1C_B	1000	ns
t_RCL	Rise time of SCL signal	Fast mode	20 + 0.1C_B	300	ns
t_FCL	Fall time of SCL signal	Standard mode	20 + 0.1C_B	300	ns
t_FCL	Fall time of SCL signal	Fast mode	20 + 0.1C_B	300	ns
t_RDA	Rise time of SDA signal	Standard mode	20 + 0.1C_B	1000	ns
t_RDA	Rise time of SDA signal	Fast mode	20 + 0.1C_B	300	ns
t_FDA	Fall time of SDA signal	Standard mode	20 + 0.1C_B	300	ns
t_FDA	Fall time of SDA signal	Fast mode	20 + 0.1C_B	300	ns
t_su;STO	Setup time for STOP condition	Standard mode	4.0		µs
t_su;STO	Setup time for STOP condition	Fast mode	600		ns
C_B	Capacitive load for SDA and SCL			0.4	nF