SWCS128A March 2015 – December 2015
PRODUCTION DATA.
- 1 Device Overview
- 2 Revision History
- 3 Pin Configuration and Functions
-
4 Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 ESD Ratings
- 4.3 Recommended Operating Conditions
- 4.4 Thermal Information
- 4.5 Electrical Characteristics: Total Current Consumption
- 4.6 Electrical Characteristics: Reference and Monitoring System
- 4.7 Electrical Characteristics: Buck Controllers
- 4.8 Electrical Characteristics: Synchronous Buck Converters
- 4.9 Electrical Characteristics: LDOs
- 4.10 Electrical Characteristics: Load Switches
- 4.11 Digital Signals: I2C Interface
- 4.12 Digital Input Signals (CTLx)
- 4.13 Digital Output Signals (IRQB, GPOx)
- 4.14 Timing Requirements
- 4.15 Switching Characteristics
- 4.16 Typical Characteristics
-
5 Detailed Description
- 5.1 Overview
- 5.2 Functional Block Diagram
- 5.3 SMPS Voltage Regulators
- 5.4 LDOs and Load Switches
- 5.5 Power Goods (PGOOD or PG) and GPOs
- 5.6 Power Sequencing and VR Control
- 5.7 Device Functional Modes
- 5.8 I2C Interface
- 5.9
Register Maps
- 5.9.1 Register Map Summary
- 5.9.2 DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = OTP-Programmable]
- 5.9.3 IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0000 0000]
- 5.9.4 IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = 1111 1111]
- 5.9.5 PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0000 0000]
- 5.9.6 SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0000 0000]
- 5.9.7 BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = OTP-Programmable]
- 5.9.8 BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = OTP-Programmable]
- 5.9.9 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = OTP-Programmable]
- 5.9.10 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = OTP-Programmable]
- 5.9.11 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = OTP-Programmable]
- 5.9.12 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP-Programmable]
- 5.9.13 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP-Programmable]
- 5.9.14 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = OTP-Programmable]
- 5.9.15 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = OTP-Programmable]
- 5.9.16 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = OTP-Programmable]
- 5.9.17 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = OTP-Programmable]
- 5.9.18 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = OTP-Programmable]
- 5.9.19 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = OTP-Programmable]
- 5.9.20 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = OTP-Programmable]
- 5.9.21 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
- 5.9.22 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = OTP-Programmable]
- 5.9.23 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = OTP-Programmable]
- 5.9.24 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = OTP-Programmable]
- 5.9.25 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = OTP-Programmable]
- 5.9.26 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = OTP-Programmable]
- 5.9.27 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = OTP-Programmable]
- 5.9.28 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP-Programmable]
- 5.9.29 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = OTP-Programmable]
- 5.9.30 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP-Programmable]
- 5.9.31 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP-Programmable]
- 5.9.32 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP-Programmable]
- 5.9.33 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = OTP-Programmable]
- 5.9.34 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = OTP-Programmable]
- 5.9.35 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = OTP-Programmable]
- 5.9.36 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = OTP-Programmable]
- 5.9.37 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = OTP-Programmable]
- 5.9.38 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = OTP-Programmable]
- 5.9.39 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = OTP-Programmable]
- 5.9.40 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = OTP-Programmable]
- 5.9.41 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = OTP-Programmable]
- 5.9.42 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = OTP-Programmable]
- 5.9.43 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = OTP-Programmable]
- 5.9.44 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = OTP-Programmable]
- 5.9.45 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = OTP-Programmable]
- 5.9.46 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = OTP-Programmable]
- 5.9.47 MISCSYSPG Register (offset = ACh) [reset = OTP-Programmable]
- 5.9.48 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP-Programmable]
- 5.9.49 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
- 5.9.50 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
- 5.9.51 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
- 5.9.52 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
- 5.9.53 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
- 5.9.54 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
- 5.9.55 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
- 6 Application and Implementation
- 7 Power Supply Coupling and Bulk Capacitors
- 8 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
1 Device Overview
1.1 Features
- Wide VIN Range From 5.6 V to 21 V
- Three Variable-Output Voltage Synchronous
Step-Down Controllers With DCAP2™ Topology- Scalable Output Current Using External FETs With Selectable Current Limit
- I2C DVS Control From 0.41 V to 1.67 V in 10-mV Steps or 1 V to 3.575 V in 25-mV Steps
- Three Variable-Output Voltage Synchronous Step-Down Converters With DCS-Control Topology
- VIN Range From 4.5 V to 5.5 V
- Up to 3 A of Output Current
- I2C DVS Control From 0.41 V to 1.67 V in 10-mV Steps or 0.425 V to 3.575 V in 25-mV Steps
- Three LDO Regulators With Adjustable Output Voltage
- LDOA1: I2C-Selectable Output Voltage From 1.35 V to 3.3 V for up to 200 mA of Output Current
- LDOA2 and LDOA3: I2C-Selectable Output Voltage From 0.7 V to 1.5 V for up to 600 mA of Output Current
- VTT LDO for DDR Memory Termination
- Three Load Switches With Slew Rate Control
- Up to 300 mA of Output Current With Voltage Drop Less Than 1.5% of Nominal Input Voltage
- RDSON < 96 mΩ at Input Voltage of 1.8 V
- 5-V Fixed-Output Voltage LDO (LDO5)
- Power Supply for Gate Drivers of SMPS and for LDOA1
- Automatic Switch to External 5-V Buck for Higher Efficiency
- Built-in Flexibility and Configurability by Factory OTP Programming
- Six GPI Pins Configurable to Enable (CTL1 to CTL6) or Sleep Mode Entry (CTL3 and CTL6) of Any Selected Rails
- Four GPO Pins Configurable to Power Good of Any Selected Rails
- Open-Drain Interrupt Output Pin
- I2C Interface Supports:
- Standard Mode (100 kHz)
- Fast Mode (400 kHz)
- Fast Mode Plus (1 MHz)
1.2 Applications
- Residential Gateway
- POS Terminals
- Test and Measurement
- Programmable Logic Controllers
- Embedded PCs
- Human to Machine Interfaces
1.3 Description
The TPS650860 device is a single-chip power-management IC designed for multicore processors, FPGAs, and other System-on-Chips (SoCs). The TPS650860 offers an input range of 5.6 V to 21 V, enabling a wide range of applications. The device is well suited for NVDC and non-NVDC power architecture using 2S, 3S, or 4S Li-Ion battery packs. See the Application Section for 5-V input supplies. The D-CAP2™ and DCS-Control high-frequency voltage regulators use small inductors and capacitors to achieve a small solution size. The D-CAP2 and DCS-Control topologies have excellent transient response performance, which is great for processor core and system memory rails that have fast load switching. An I2C interface allows simple control either by an embedded controller (EC) or by an SoC. The PMIC comes in an
8-mm × 8-mm, single-row VQFN package with thermal pad for good thermal dissipation and ease of board routing.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TPS650860 | VQFN (64) | 8.00 mm × 8.00 mm |
(1) For more information, see the Mechanical Packaging and Orderable Information section.
1.4 Functional Block Diagram
