ZHCSI59I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Device Options
- 7 Pin Configuration and Functions
-
8 Specifications
- 8.1 Absolute Maximum Ratings
- 8.2 ESD Ratings
- 8.3 Recommended Operating Conditions
- 8.4 Thermal Information
- 8.5 Electrical Characteristics
- 8.6 Electrical Characteristics - DCDC1 Converter
- 8.7 Electrical Characteristics - DCDC2 Converter
- 8.8 Electrical Characteristics - DCDC3 Converter
- 8.9 Electrical Characteristics - VLDO1 and VLDO2 Low Dropout Regulators
- 8.10 Electrical Characteristics - wLED Boost Converter
- 8.11 Electrical Characteristics - Reset, PB_IN, PB_OUT, PGood, Power_on, INT, EN_EXTLDO, EN_wLED
- 8.12 Electrical Characteristics - ADC Converter
- 8.13 Electrical Characteristics - Touch Screen Interface
- 8.14 Electrical Characteristics - Power Path
- 8.15 Electrical Characteristics - Battery Charger
- 8.16 Timing Requirements
- 8.17 Dissipation Ratings
- 8.18 Typical Characteristics
- 9 Parameter Measurement Information
-
10Detailed Description
- 10.1 Overview
- 10.2 Functional Block Diagram
- 10.3
Feature Description
- 10.3.1 Battery Charger and Power Path
- 10.3.2 Power Down
- 10.3.3 Power-On Reset
- 10.3.4 Power-Path Management
- 10.3.5 Battery Charging
- 10.3.6 Battery Pack Temperature Monitoring
- 10.3.7 Battery Charger State Diagram
- 10.3.8 DC-DC Converters and LDOs
- 10.3.9 Power Save Mode
- 10.3.10 Short-Circuit Protection
- 10.3.11 Enable
- 10.3.12 Short-Circuit Protection
- 10.3.13 Thermal Shutdown
- 10.4 Device Functional Modes
- 10.5 Programming
- 10.6
Register Maps
- 10.6.1 PPATH1. Register Address: 01h
- 10.6.2 INT. Register Address: 02h
- 10.6.3 CHGCONFIG0. Register Address: 03h
- 10.6.4 CHGCONFIG1. Register Address: 04h
- 10.6.5 CHGCONFIG2. Register Address: 05h
- 10.6.6 CHGCONFIG3. Register Address: 06h
- 10.6.7 ADCONFIG. Register Address: 07h
- 10.6.8 TSCMODE. Register Address: 08h
- 10.6.9 ADRESULT_1. Register Address: 09h
- 10.6.10 ADRESULT_2. Register Address: 0Ah
- 10.6.11 PGOOD. Register Address: 0Bh
- 10.6.12 PGOODMASK. Register Address: 0Ch
- 10.6.13 CON_CTRL1. Register Address: 0Dh
- 10.6.14 CON_CTRL2. Register Address: 0Eh
- 10.6.15 CON_CTRL3. Register Address: 0Fh
- 10.6.16 DEFDCDC1. Register Address: 10h
- 10.6.17 DEFDCDC2_LOW. Register Address: 11h
- 10.6.18 DEFDCDC2_HIGH. Register Address: 12h
- 10.6.19 DEFDCDC3_LOW. Register Address: 13h
- 10.6.20 DEFDCDC3_HIGH. Register Address: 14h
- 10.6.21 DEFSLEW. Register Address: 15h
- 10.6.22 LDO_CTRL1. Register Address: 16h
- 10.6.23 DEFLDO2. Register Address: 17h
- 10.6.24 WLED_CTRL1. Register Address: 18h
- 10.6.25 WLED_CTRL2. Register Address: 19h
-
11Application and Implementation
- 11.1 Application Information
- 11.2
Typical Applications
- 11.2.1 General PMIC Application
- 11.2.2 Powering OMAP-L138
- 11.2.3 Powering Atlas IV
- 11.2.4 OMAP35xx (Supporting SYS-OFF Mode)
- 11.2.5 TPS650731 for OMAP35xx
- 11.2.6 Powering AM3505 Using TPS650732
- 12Power Supply Recommendations
- 13Layout
- 14器件和文檔支持
- 15機械、封裝和可訂購信息
10.5.1.1 Serial interface
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. The TPS6507x has a 7-Bit address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from register addresses not listed in this section will result in 00h being read out. For normal data transfer, SDAT is allowed to change only when SCLK is low. Changes when SCLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per Bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the device generates an acknowledge Bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge Bit. The TPS6507x device must pull down the SDAT line during the acknowledge clock pulse so that the SDAT line is a stable low during the high period of the acknowledge clock pulse. The SDAT line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge Bit on the last byte that was clocked out of the slave. In this case, the slave TPS6507x device must leave the data line high to enable the master to generate the stop condition.
All registers are set to their default value by one of these conditions:
- Voltage is below the UVLO threshold defined with registers <UVLO1>, <UVLO0>
- PB_IN is asserted LOW for >15s (option)
Figure 40. Bit Transfer on the Serial Interface 
Figure 41. START and STOP Conditions 
Figure 42. Serial Interface WRITE to TPS6507x 
Figure 43. Serial Interface READ from TPS6507x: Protocol A 
Figure 44. Serial Interface READ from TPS6507x: Protocol B