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SLVS844A September 2008 – June 2015 TPS65055

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RSM|32
- MPQF195B

散熱焊盤機械數據 (封裝 | 引腳)

RSM|32
- QFND112H

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
	Input voltage range on all pins except A/PGND, EN_LDO1 pins with respect to AGND	–0.3	7	V
	Input voltage range on EN_LDO1 pins with respect to AGND	–0.3	V_CC+0.5	V
	Output voltage range on LDO1, LDO2, LDO3, LDO4 pins with respect to AGND	–0.3	4	V
	Current at VINDCDC1/2, L1, PGND1, L2, PGND2		1800	mA
	Current at all other pins		1000	mA
	Continuous total power dissipation	See Dissipation Ratings
T_A	Operating free-air temperature	–40	85	°C
T_J	Maximum junction temperature		125	°C
	Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds		260	°C
T_st	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges; HBM according to EIA/JESD22-A114-B: 1.5 kV; and CDM according EIA/JESD22C101C: 500 V, however, it is advised that precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_INDCDC1/2	Input voltage range for step-down converters	2.5	4	6	V
V_DCDC1	Output voltage range for VDCDC1 step-down converter	0.6		V_INDCDC1	V
V_DCDC2	Output voltage range for VDCDC2 step-down converter	0.6		V_INDCDC2	V
V_INLDO1, V_INLDO2, V_INLDO3/4	Input voltage range for LDOs	1.5		6.5	V
V_LDO1-3	Output voltage range for LDO1 and LDO3	0.8		2.8	V
V_LDO2-4	Output voltage range for LDO2 and LDO4	1		3	V
I_OUTDCDC1	Output current at L1			600	mA
L1	Inductor at L1⁽¹⁾	1.5	2.2		μH
C_INDCDC1/2	Input capacitor at VINDCDC1/2⁽¹⁾	22			μF
C_OUTDCDC1	Output capacitor at VDCDC1⁽¹⁾	10	22		μF
I_OUTDCDC2	Output current at L2			600	mA
L2	Inductor at L2⁽¹⁾	1.5	2.2		μH
C_OUTDCDC2	Output capacitor at VDCDC2⁽¹⁾	10	22		μF
C_VCC	Input capacitor at VCC ⁽¹⁾	1			μF
C_in1-2	Input capacitor at VINLDO1/2⁽¹⁾	2.2			μF
C_in3-4	Input capacitor at VINLDO3/4⁽¹⁾	2.2			μF
C_OUT1-2	Output capacitor at VLDO1-4⁽¹⁾	2.2			μF
I_LDO1,2	Output current at VLDO1,2			400	mA
I_LDO3,4	Output current at VLDO3,4			200	mA
T_A	Operating ambient temperature	–40		85	°C
T_J	Operating junction temperature	–40		125	°C
R_CC	Resistor from battery voltage to V_cc used for filtering⁽²⁾		1	10	Ω

(1) See Application and Implementation for more details.

(2) Up to 2 mA can flow into V_cc when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted accordingly.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS65055	UNIT
		RSM [VQFN]
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	37.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	30.1	°C/W
R_θJB	Junction-to-board thermal resistance	7.8	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	7.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

V_IN = 3.6 V, EN = V_IN, MODE = GND, L = 2.2 μH, C_OUT = 22 μF, T_A = –40°C to 85°C, Typical values are at T_A = 25°C (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
V_cc	Input voltage range			2.5		6	V
I_Q	Operating quiescent current Total current into V_CC, VINDCDC1/2, VINLDO1, VINLDO2, VINLDO3/4		One converter, I_OUT = 0 mA. PFM mode enabled; device not switching, EN_DCDC1 = V_IN or EN_DCDC2 = V_IN; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND		30	40	μA
			Two converters, I_OUT = 0 mA, PFM mode device not switching, EN_DCDC1 = V_IN and EN_DCDC2 = V_IN; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND		40	55	μA
			One converter, I_OUT = 0 mA, PFM mode enabled; device not switching, EN_DCDC1 = V_IN or EN_DCDC2 = V_IN; EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = V_IN		190	260	μA
I_Q	Operating quiescent current into V_CC		One converter, I_OUT = 0 mA, Switching with no load, PWM operation EN_DCDC1 = V_IN or EN_DCDC2 = V_IN; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND		0.85		mA
I_Q	Operating quiescent current into V_CC		Two converters, I_OUT = 0 mA, Switching with no load, PWM operation EN_DCDC1 = V_INAND EN_DCDC2 = V_IN; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND		1.25		mA
I_(SD)	Shutdown current		EN_DCDC1 = EN_DCDC2 = GND EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = GND		18	22	μA
V_(UVLO)	Undervoltage lockout threshold for DCDC converters and LDOs		Voltage at V_CC		1.8	2	V
EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4
V_IH	High-level input voltage, SDAT, SCLK, EN_DCDC1, EN_DCDC2, DEFDCDC2, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4			1.2		V_CC	V
V_IL	Low-level input voltage SDAT, SCLK, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4, DEFDCDC2			0		0.4	V
I_IN	Input bias current SDAT, SCLK, EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4				0.01	1	μA
V_IH	DEFLDO1, DEFLDO2		V_CC = 2.5 V	1.0			V
V_IL	DEFLDO1, DEFLDO2		V_CC = 6.5 V			0.38	V
RPD	Pulldown resistor at DEFLDO1, DEFLDO2 for LOW signal		Pulled to GND			1	kΩ
RPU	Pullup resistor at DEFLDO1, DEFLDO2 for HIGH signal		Pulled to V_CC			1	kΩ
RGNDopen	Resistance at DEFLDO1, DEFLDO2 to GND to detect open state			10			MΩ
RVCCopen	Resistance at DEFLDO1, DEFLDO2 to Vcc to detect open state			20			MΩ
POWER SWITCH
r_DS(on)	P-channel MOSFET on resistance	DCDC1, DCDC2	VINDCDC1/2 = 3.6 V		280	630	mΩ
r_DS(on)	P-channel MOSFET on resistance	DCDC1, DCDC2	VINDCDC1/2 = 2.5 V		400		mΩ
I_{LD_PMOS}	P-channel leakage current		V_DS = 6 V			1	μA
r_DS(on)	N-channel MOSFET on resistance	DCDC1, DCDC2	VINDCDC1/2 = 3.6 V		220	450	mΩ
r_DS(on)	N-channel MOSFET on resistance	DCDC1, DCDC2	VINDCDC1/2 = 2.5 V		320		mΩ
I_{LK_NMOS}	N-channel leakage current		V_DS = 6 V		7	10	μA
I_(LIMF)	Forward current limit PMOS (high-side) and NMOS (low side)	DCDC1	2.5 V ≤ V_IN ≤ 6 V	0.85	1.0	1.15	A
I_(LIMF)	Forward current limit PMOS (high-side) and NMOS (low side)	DCDC2	2.5 V ≤ V_IN ≤ 6 V	0.85	1.0	1.15	A
T_SD	Thermal shutdown		Increasing junction temperature		150		°C
	Thermal shutdown hysteresis		Decreasing junction temperature		20		°C
OSCILLATOR
f_SW	Oscillator frequency			2.025	2.25	2.475	MHz
OUTPUT
V_OUT	Output voltage range			0.8		V_IN	V
V_OUT	DC output voltage accuracy	DCDC1, DCDC2⁽¹⁾	V_IN = 2.5 V to 6 V, Mode = GND, PFM operation, 0 mA < I_OUT < I_OUTMAX	–1.5%	0%	3.5%
V_OUT	DC output voltage accuracy	DCDC1, DCDC2⁽¹⁾	V_IN = 2.5 V to 6 V, Mode = V_IN, PWM operation, 0 mA < I_OUT < I_OUTMAX	–1.5%	0%	1.5%
ΔV_OUT	Power save mode ripple voltage⁽²⁾		I_OUT = 1 mA, PFM = GND, Bandwidth = 20 MHz		25		mV_PP
t_Start	Start-up time		Time from active EN to start switching		170		μs
t_Ramp	V_OUT Ramp up time		Time to ramp from 5% to 95% of V_OUT		750		μs
R_DIS	Internal discharge resistor at L1, L2				350		Ω
V_OL	RST, DPD, discharge output low voltage		I_OL = 1 mA, V_threshold < 0.8 V			0.3	V
I_OL	RST, DPD sink current			1			mA
I_OL	discharge sink current			10			mA
	RST, DPD, discharge output leakage current		V_threshold > 0.8 V, RST and DPD outputs turned off (internal NMOS in high impedance state)		0.01	1	μA
V_th	V_threshold voltage		Voltage rising	0.78	0.8	0.82	V
	Hysteresis on threshold		Voltage decreasing		80		mV
VLDO1, VLDO2, VLDO3 and VLDO4 LOW DROPOUT REGULATORS
V_INLDO	Input voltage range for LDO1, LDO2, LDO3, LDO4			1.5		6.5	V
V_LDO1	LDO1 output voltage range			0.8		2.8	V
V_LDO2	LDO2 output voltage range			1.2		3	V
V_LDO3	LDO3 output voltage			0.8		2.8	V
V_LDO4	LDO4 output voltage range			1.2		3	V
I_O	Maximum output current for LDO1,LDO2			400			mA
I_O	Maximum output current for LDO3, LDO4			200			mA
I_(SC)	LDO1 and LDO2 short-circuit current limit		V_LDO1 = GND, V_LDO2 = GND			800	mA
I_(SC)	LDO3 and LDO4 short-circuit current limit		V_LDO3 = GND, V_LDO4 = GND			400	mA
	Dropout voltage at LDO1		I_O = 250 mA, V_INLDO = 1.8 V			600	mV
	Dropout voltage at LDO2		I_O = 400 mA, V_INLDO = 3.3 V			450	mV
	Dropout voltage at LDO3, LDO4		I_O = 200 mA, V_INLDO = 1.8 V			280	mV
	Output voltage accuracy for LDO1, LDO2, LDO3		I_O = 10 mA	–2%		1%
	Leakage current from V_INLDOx to V_LDOx		LDO enabled, V_INLDOx = 6.5 V; V_O = 1.0 V, T = 140°C		3		μA
	Output voltage accuracy for LDO1, LDO2, LDO3, LDO4		I_O = 10 mA	–2%		1%
	Line regulation for LDO1, LDO2, LDO3, LDO4		V_INLDO1,2 = V_LDO1,2 + 0.5 V (minimum 2.5 V) to 6.5 V, V_INLDO3,4 = V_LDO3,4 + 0.5 V (minimum 2.5 V) to 6.5 V, I_O = 10 mA	–1%		1%
	Load regulation for LDO1, LDO2, LDO3, LDO4		I_O = 0mA to 400 mA for LDO1, LDO2 I_O = 0mA to 200 mA for LDO3, LDO4	–1%		1%
	Regulation time for LDO1, LDO2, LDO3, LDO4		Load change from 10% to 90%		10		μs
PSRR	Power supply rejection ratio		f = 10 kHz; I_O = 50 mA; V_I = V_O + 1 V		70		dB
R_DIS	Internal discharge resistor at VLDO1, VLDO2, VLDO3, VLDO4				350		Ω
T_SD	Thermal shutdown		Increasing junction temperature		140		°C
	Thermal shutdown hysteresis		Decreasing junction temperature		20		°C

(1) Output voltage specification does not include tolerance of external voltage programming resistors.

(2) In power save mode, PWM operation is typically entered at IPSM = VIN/32 ?.

6.6 Dissipation Ratings

PACKAGE	R_θJA	T_A ≤ 25°C POWER RATING	DERATING FACTOR ABOVE T_A = 25°C	T_A = 70°C POWER RATING	T_A = 85°C POWER RATING
RSM⁽¹⁾	58 K/W	1.7 W	17 mW/K	0.95 W	0.68 W

(1) The thermal resistance junction-to-case of the RSM package is 4 K/W measured on a high K board.

6.7 Typical Characteristics

Table 1. Table Of Graphs

			FIGURE
η	Efficiency DCDC1 (V_O = 2.1 V)	vs Load current / PWM mode	Figure 1
η	Efficiency DCDC1 (V_O = 2.1 V)	vs Load current / PFM mode	Figure 2
η	Efficiency DCDC2 (V_O = 1.575 V)	vs Load current / PWM mode	Figure 3
η	Efficiency DCDC2 (V_O = 1.575 V)	vs Load current / PFM mode	Figure 4
η	Efficiency DCDC2 (V_O = 1.2 V)	vs Load current / PWM mode	Figure 5
η	Efficiency DCDC2 (V_O = 1.2 V)	vs Load current / PFM mode	Figure 6
	Output voltage ripple in PFM mode	Scope plot	Figure 7
	Output voltage ripple in PWM mode	Scope plot	Figure 8
	Startup timing DCDC1, DCDC2, LDO1	Scope plot	Figure 9
	Startup timing LDO1, LDO2, LDO3, LDO4	Scope plot	Figure 10
	Load transient response DCDC1; PWM	Scope plot	Figure 11
	Load transient response DCDC1; PFM	Scope plot	Figure 12
	Load transient response DCDC2; PWM	Scope plot	Figure 13
	Load transient response DCDC2;PFM	Scope plot	Figure 14
	Line transient response DCDC1 (V_O = 2.1 V)	Scope plot	Figure 15
	Line transient response DCDC2 (V_O = 1.2 V)	Scope plot	Figure 16
	Load transient response LDO1	Scope plot	Figure 17
	Load transient response LDO4	Scope plot	Figure 18
	Line transient response LDO1	Scope plot	Figure 19