8.3.1 Step-Down Converters, VDCDC1, VDCDC2 and VDCDC3

The TPS65024x devices incorporate three synchronous step-down converters operating typically at 2.25-MHz fixed-frequency pulse width modulation (PWM) for moderate to heavy-load currents. At light-load currents the converters automatically enter power save mode and operate with pulse frequency modulation (PFM). The maximum supported load currents for VDCDC1 and VDCDC2 are device specific, unlike VDCDC3 which does not have the capability to exceed an 800-mA output.

The converter output voltages can be programmed through the DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins. The pins can often be connected to GND, V_CC, or to a resistor divider between the output voltage and GND.

The VDCDC1 converter defaults to 2.80 V or 3.3 V depending on the DEFDCDC1 configuration pin, if DEFDCDC1 is tied to ground the default is 2.80 V, if it is tied to V_CC the default is 3.3 V. When the DEFDCDC1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. Reference the Output Voltage Selection section for details on setting the output voltage range.

The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin, if DEFDCDC2 is tied to ground the default is 1.8 V, if it is tied to V_CC the default is 2.5 V. When the DEFDCDC2 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.

The VDCDC3 converter defaults to 1.0 V or 1.3 V for the TPS650240 depending on the DEFDCDC3 configuration pin, if DEFDCDC3 is tied to ground the default is 1.0 V, if it is tied to V_CC the default is 1.3 V. The DEFDCDC3 pin cannot be connected to a resistor divider. In opposition to DEFDCDC1 and DEFDCDC2, the DEFDCDC3 pin can be used to change the core voltage during operation by changing its logic level from HIGH to LOW or vice versa. TPS650241 to TPS650245 allow different voltages for the VDCDC3 converter. Reference the Voltage Options section for the TPS650240, TPS650241, TPS650242, TPS650243, TPS650244, and TPS650245 default voltage options.

During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feedforward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the adaptive dead-time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch.

The three DC–DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A 180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3 switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the VDCDC2 converter from 3.7 V to 2.5 V and the VDCDC3 converter from 3.7 V to 1.5 V.

8.4.1 Power Save Mode Operation

As the load current decreases, the converters enter power save mode operation. During power save mode the converters operate in a burst mode (PFM mode) with a frequency between 1.125 MHz and 2.25 MHz for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency, with a minimum quiescent current to maintain high efficiency.

To optimize the converter efficiency at light load, the average current is monitored, and if in PWM mode, the inductor current remains below a certain threshold before the device enters power save mode. The typical threshold to enter power save mode can be calculated in Equation 1, Equation 2, and Equation 3:

Equation 1.

Equation 2.

Equation 3.

During power save mode the output voltage is monitored with a comparator and by maximum skip burst width. As the output voltage falls below the threshold, set to the nominal V_O, the P-channel switch turns on and the converter effectively delivers a constant current as defined in Equation 4, Equation 5, and Equation 6.

Equation 4.

Equation 5.

Equation 6.

If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode if either of the following conditions are met:

1. The output voltage drops 2% below the nominal V_O due to increased load current
2. The PFM burst time exceeds 16 × 1 / fs (7.1 μs typical)

These control methods reduce the quiescent current to typically 14 μA per converter and the switching activity to a minimum thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light-load current results in a very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values makes the output ripple tend to zero. Power save mode can be disabled by pulling the MODE pin high. This forces all DC–DC converters into fixed-frequency PWM mode.

8.4.2 Soft-Start

Each of the three converters has an internal soft-start circuit that limits the inrush current during start-up. The soft-start is realized by using a very low current to initially charge the internal compensation capacitor. The soft-start time is typically 750 μs if the output voltage ramps from 5% to 95% of the final target value. If the output is already precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a short delay of typically 170 μs between the converter being enabled and switching activity actually starting. This is to allow the converter to bias itself properly, to recognize if the output is precharged, and if so, to prevent discharging of the output while the internal soft-start ramp catches up with the output voltage.

8.4.3 100% Duty Cycle Low-Dropout Operation

The TPS65024x converters offer a low input-to-output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load current and output voltage and can be calculated in Equation 7.

Equation 7.

where

• Iout_max = Maximum load current (note: ripple current in the inductor is zero under these conditions)
• RDSon_max = Maximum P-channel switch RDSon
• R_L = DC resistance of the inductor
• Vout_min = Nominal output voltage minus 2% tolerance limit

8.4.4 Low-Dropout Voltage Regulators

The low-dropout voltage regulators are designed to operate well with low-value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 300 mV at the rated output current. Each LDO sports a current limit feature. Both LDOs are enabled by the EN_LDO pin. The LDOs also have reverse conduction prevention. This allows the possibility to connect external regulators in parallel in systems with a backup battery. The TPS65024x step-down and LDO voltage regulators automatically power down when the V_CC voltage drops below the UVLO threshold or when the junction temperature rises above 160°C.

8.4.5 Undervoltage Lockout

The undervoltage lockout circuit for the five regulators on the TPS65024x prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The UVLO circuit monitors the V_CC pin; the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis.

See VCC Filter for details on the external RC filter.

8.4.6 Power-Up Sequencing

The TPS65024x power-up sequencing is designed to be entirely flexible and customer driven; this is achieved simply by providing separate enable pins for each switch-mode converter and a common enable signal for LDO1 and LDO2. The relevant control pins are described in Table 2.

8.4.7 PWRFAIL

The PWRFAIL signal is generated by a voltage detector at the PWRFAIL_SNS input. The input signal is compared to a 1-V threshold (falling edge) with 5% (50 mV) hysteresis. PWRFAIL is an open-drain output which is actively low when the input voltage at PWRFAIL_SNS is below the threshold.