7.3.1 Step-Down Converters, VMAIN and VCORE

The TPS65014 incorporates two synchronous step-down converters operating typically at 1.25-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter power-save mode and operate with pulse frequency modulation (PFM). The main converter is capable of delivering 1-A output current and the core converter is capable of delivering 400 mA.

The converter output voltages are programmed through the VDCDC1 and VDCDC2 registers in the serial interface. The main converter defaults to 3-V or 3.3-V output voltage depending on the DEFMAIN configuration pin, if DEFMAIN is tied to ground, the default is 3 V; if it is tied to V_CC, the default is 3.3 V. The core converter defaults to either 1.5 V or 1.8 V, depending on whether the DEFCORE configuration pin is tied to GND or to V_CC, respectively. Both the main and core output voltages can subsequently be reprogrammed after start-up through the serial interface. In addition, the LOW_PWR pin can be used either to lower the core voltage to a value defined in the VDCDC2 register when the application processor is in deep sleep mode, or to disable the core converter. An active signal at LOW_PWR is ignored if the ENABLE_LP bit is not set in the VDCDC1 register.

The step-down converter outputs (when enabled) are monitored by power-good comparators, the outputs of which are available through the serial interface. The outputs of the DC-DC converters can be optionally discharged when the DC-DC converters are disabled.

During PWM operation, the converters use a fast response voltage-mode controller scheme with input voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle, initiated by the clock signal, the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch.

The error amplifier, together with the input voltage, determines the rise time of the saw-tooth generator, and therefore any change in input voltage or output voltage directly controls the duty cycle of the converter, giving a good line and load transient regulation.

The two DC-DC converters operate synchronized to each other, with the MAIN converter as the master. A 270° phase shift between the MAIN switch turnon and the CORE switch turnon decreases the input RMS current, and smaller input capacitors can be used. This is optimized for a typical application where the MAIN converter regulates a Li-ion battery voltage of 3.7 V to 3.3 V and the CORE from 3.7 V to 1.5 V.

7.3.1.4 100% Duty Cycle Low Dropout Operation

The TPS65014 converters offer a low input to output voltage difference while maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage and is calculated in Equation 1:

Equation 1.

where

• I_O(max) = maximum output current plus inductor ripple current
• r_DS(on)max = maximum P-channel switch r_DSon
• R_L = DC resistance of the inductor
• V_O(max) = nominal output voltage plus maximum output voltage tolerance

7.3.2 Low-Dropout Voltage Regulators

The low-dropout voltage regulators are designed to operate with low value ceramic input and output capacitors. They operate with input voltages down to 1.8 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO has a current limit feature. Both LDOs are enabled per default; both LDOs can be disabled or programmed through the serial interface using the VREGS1 register. The LDO outputs (when enabled) are monitored by power-good comparators, the outputs of which are available through the serial interface. The LDOs also have reverse conduction prevention when disabled. This allows the possibility to connect external regulators in parallel in systems with a backup battery.

7.3.3 Undervoltage Lockout

The undervoltage lockout circuit for the four regulators on TPS65014 prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. Basically, it prevents the converter from turning on the power switch or rectifier FET under undefined conditions. The undervoltage threshold voltage is set by default to 2.75 V. After power up, the threshold voltage can be reprogrammed through the serial interface. The undervoltage lockout comparator compares the voltage on the VCC pin with the UVLO threshold. When the VCC voltage drops below this threshold, the TPS65014 sets the PWRFAIL pin low and after a time t_(UVLO) disables the voltage regulators in the sequence defined by PS_SEQ. The same procedure is followed when the TPS65014 detects that its junction temperature has exceeded the overtemperature threshold, typically 160°C, with a delay t_(overtemp). The TPS65014 automatically restarts when the UVLO (or overtemperature) condition is no longer present.

The battery charger circuit has a separate UVLO circuit with a threshold of typically 2.5 V, which is compared with the voltage on AC and USB supply pins.

7.3.4 Power-Up Sequencing

The TPS65014 power-up sequencing is designed to allow the maximum flexibility without generating excessive logistical or system complexity. The relevant control pins are described in Table 2.

Figure 23. TPS65014 Power-On State Diagram

7.3.4.1 TPS65014 Power State Descriptions

7.3.4.1.1 State 1: No Power

No batteries are connected to the TPS65014. When main power is applied, the bandgap reference, LDOs, and UVLO comparator start up. The RESPWRON, PWRFAIL, INT, and MPU_RESET signals are held low. When BATT_COVER goes high (de-bounced internally by the TPS65014), indicating that the battery cover has been put in place and if VCC > UVLO, the power supplies are ramped in the sequence defined by PS_SEQ. RESPWRON, PWRFAIL, INT, and MPU_RESET are released when the RESPWRON timer has timed out after t_n(RESPWRON) seconds. If VCC remains valid and no OVERTEMP condition occurs, then the TPS65014 arrives in State 2: ON. If VCC < UVLO, the TPS65014 keeps the bandgap reference and UVLO comparator active such that when VCC>UVLO (during battery charge), the supplies are automatically activated.

7.3.4.1.2 State 2: ON

In this state, the TPS65014 is fired up and ready for operation. The switching converter output voltages can be programmed. The LDOs can be disabled or programmed. The TPS65014 can exit this state due to an overtemperature condition, an undervoltage condition at VCC, BATT_COVER going low, or by the processor programming low power mode. State 2 is left temporarily if the user activates the HOT_RESET pin.

7.3.4.1.3 State 3: Low-Power Mode

This state is entered through the processor setting the ENABLE_LP bit in the serial interface and then raising the LOW_PWR pin. The TPS65014 uses the rising edge of the internal signal formed by a logical AND of the LOW_PWR and ENABLE LP signals to enter low power mode. The VMAIN switching converter remains active, but the VCORE converter may be disabled in low power mode through the serial interface by setting the LP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltage is set to the value predefined by the CORELP0/1 bits in the VDCDC2 register. The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1 register determine whether the LDOs are turned off or put in a reduced power mode (transient speed-up circuitry disabled in order to minimize quiescent current) in low power mode. All TPS65014 features remain addressable through the serial interface. The TPS65014 can exit this state either due to an undervoltage condition at VCC, due to BATT_COVER going low, due to an OVERTEMP condition, by the processor deasserting the LOW_POWER pin, or by the user activating the HOT_RESET pin or the PB_ONOFF pin.

7.3.4.1.4 State 4: Shutdown

There are two scenarios for entering this state. The first is from State 1: No Power. As soon as main battery power is applied, the device automatically enters the WAIT mode.

The second scenario occurs when the device is in ON mode and the processor initiates a shutdown by resetting the ENABLE SUPPLY bit in the VDCDC1 register (ENABLE_LP must be high), and then raising the LOW_PWR pin. When this happens, the power rails are ramped down in the predefined sequence, and all circuitry is then disabled. In this state, the TPS65014 waits for the PB_ONOFF or HOT_RESET pin to be activated before enabling any of the supply rails. When the PB_ONOFF or HOT_RESET pin is activated, the TPS65014 powers up the supplies according to the same constraints as at the initial application of power. Complete shutdown is only achieved by setting the LDO1OFF/nSLP and LDO2OFF/nSLP bits high in the VREGS1 register before activating the shutdown.

In this case, the I²C interface is deactivated, and the registers are reset to their default value after leaving the WAIT mode.

To enter the WAIT mode when USB or AC is present, set the AUA bit (CHCONFIG<7>). The WAIT mode is automatically left if bit 7 in register CHCONFIG is set to 0 (default), and a voltage is present at either the AC pin or the USB pin in the appropriate range for charging, and the voltage at V_CC is above the UVLO threshold. This feature allows the converters to start up automatically if the device is plugged in for charging.

If all supplies are turned off in WAIT mode, the internal bandgap is switched off, and the internal registers are reset to their default state when the device returns to ON mode.

Table 3 lists possible configurations in LOW POWER mode and WAIT mode.

Table 3. TPS65014 Possible Configurations⁽¹⁾

CONVERTER	MAIN	CORE	LDO1	LDO2
LOW POWER mode	1	0/1	0/1	0/1
WAIT mode	0	0	0/1	0/1

(1) 0 = converter is disabled
1 = converter is enabled

Table 4 indicates the typical quiescent-current consumption in each power state.

Table 4. TPS65014 Typical Current Consumption

STATE	TOTAL QUIESCENT CURRENT	QUIESCENT CURRENT BREAKDOWN
1	0
2	30 µA–70 µA	VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference + PowerGood
3	30 µA–55 µA	VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference + PowerGood
4	13 µA	UVLO + reference circuitry

NOTE:

Valid for LDO1 supplied from VMAIN as described earlier in this Application Section.

Figure 24. State 1 to State 2 Transition (PS_SEQ = 0, V_CC > V_UVLO + HYST)

If 2.4 ms after application V_CC is still below the default UVLO threshold (3.15 V for V_CC rising), then start up is as shown in Figure 25.

NOTE:

Valid for LDO1 supplied from VMAIN as described earlier in this Application Section

Figure 25. State 1 to State 4 to State 2 Transition (Power-Up Behavior When Charge Voltage is Applied)

NOTE:

Valid for LDO1 supplied from VMAIN as described earlier in this Application Section

Figure 26. State 2 to State 4 Transition

NOTE:

VCORE Lowered, LDO2 Disabled

NOTE:

Subsequent State 3 to State 2 Transition When LOW POWER Is Deasserted.

Figure 27. State 2 to State 3 Transition

NOTE:

PB_ONFF Activated (See Interrupt Management for INT Behavior)

Figure 28. State 3 to State 2 Transition

NOTE:

HOT_RESET Activated (See Interrupt Management for INT Behavior)

Figure 29. State 3 to State 2 Transition

Figure 30. State 1 to State 4 Transition

7.3.5 System Reset and Control Signals

The RESPWRON signal is used as a global reset for the application. It is an open-drain output. The RESPWRON signal is generated according to the power good comparator linked to VMAIN and remains low for t_n(RESPWRON) seconds after VMAIN has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET, and INT are also held low.

If the output voltage of MAIN is less than 90% of its nominal value, as RESPWRON is generated, and if the output voltage of MAIN is programmed to a higher value, which causes the output voltage to fall out of the 90% window, then a RESPWRON signal is generated.

The PWRFAIL signal indicates when VCC < UVLO or when the TPS65014 junction temperature has exceeded a reliable value or if BATT_COVER is taken low. This open-drain output can be connected at a fast interrupt pin for immediate attention by the application processor. All supplies are disabled t_(uvlo), t_(overtemp), or t_{(batt_cover)} seconds after PWRFAIL has gone low, giving time for the application processor to shut down cleanly.

BATT_COVER is used to detect whether the battery cover is in place or not. If the battery cover is removed, the TPS65014 generates a warning to the processor that the battery is likely to be removed and that it may be prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER has an internal 2-MΩ pulldown resistor.

The HOT_RESET input is used to generate an MPU_RESET signal for the application processor. The HOT_RESET pin could be connected to a user-activated button in the application. It can also be used to exit low power mode. In this case, the TPS65014 waits until the VCORE voltage has stabilized before generating the MPU_RESET pulse. The MPU_RESET pulse is active low for t_{(mpu_nreset)} seconds. HOT_RESET has an internal 1-MΩ pullup resistor to V_CC.

The PB_ONOFF input can be used to exit LOW POWER MODE. It is typically driven by a user-activated pushbutton in the application. Both HOT_RESET and PB_ONOFF are de-bounced internally by the TPS65014. Typical debounce time is 56 ms. PB_ONOFF has an internal 1-MΩ pulldown resistor.

PB_ONOFF, BATT_COVER and UVLO events also cause a normal, maskable interrupt to be generated and are noted in the REGSTATUS register.

7.3.6 Vibrator Driver

The VIB open-drain output is provided to drive a vibrator motor, controlled through the serial interface register VDCDC2. It has a maximum dropout of 0.5 V at 100-mA load. Typically, an external resistor is required to limit the motor current and a freewheel diode to limit the VIB overshoot voltage at turnoff.

7.3.7 LED2 Output

The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off. The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum blink-on time is 10 ms, and this can be increased in 127 10-ms steps to 1280 ms. For both PG and LED2, the minimum blink period is 100 ms, and this can be increased in 127 100-ms steps to 12800 ms.

7.3.8 Interrupt Management

The open-drain INT pin is used to combine and report all possible conditions through a single pin. Battery and chip temperature faults, precharge timeout, charge timeout, taper timeout, and termination current are each capable of setting INT low, that is, active. INT can also be activated if any of the regulators are below the regulation threshold. Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can be programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to mask an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2, or MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS, REGSTATUS, and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are acknowledged by reading these registers. If a 1 is present in any location, then the TPS65014 automatically sets the corresponding bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register contents are self-clearing when the condition, which caused the interrupt, is removed. The applications processor should not normally need to access the ACKINT1 or ACKINT2 registers.

Interrupt events are always captured; thus when an interrupt source is unmasked, INT may immediately go active due to a previous interrupt condition. This can be prevented by first reading the relevant STATUS register before unmasking the interrupt source.

If an interrupt condition occurs, then the INT pin is set low. The CHGSTATUS, REGSTATUS, and DEFGPIO registers should be read. Bit positions containing a 1 (or possibly a 0 in DEFGPIO) are noted by the CPU and the corresponding situation resolved. The reading of the CHGSTATUS and REGSTATUS registers automatically acknowledges any interrupt condition in those registers and blocks the path to the INT pin from the relevant bits. No interrupt should be missed during the read process because this process starts by latching the contents of the register before shifting them out at SDAT. Once the contents have been latched (which takes a couple of nanoseconds), the register is free to capture new interrupt conditions. Thus, for practical purposes the probability of missing anything is zero.

The following describes how registers 0x01 (CHGSTATUS) and 0x02 (REGSTATUS) are handled:

• CHGSTATUS(5,0) are positive edge set. Read of set CHGSTATUS(5,0) bits sets ACKINT1(5,0) bits.
• CHGSTATUS(7-6,4-1) are level set. Read of set CHGSTATUS(7-6,4-1) bits sets ACKINT1(7-6,4-1) bits.
• CHGSTATUS(5,0) clear when input signal low, and ACKINT1(5,0) bits are already set.
• CHGSTATUS(7-6,4-1) clear when input signal is low.
• ACKINT1(7-0) clear when CHGSTATUS(7-0) is clear.
• REGSTATUS(7-5) are positive edge set. Read of set REGSTATUS(7-5) bits sets ACKINT2(7-5) bits.
• REGSTATUS(3-0) are level set. Read of set REGSTATUS(3-0) bits sets ACKINT2(3-0) bits.
• REGSTATUS(7-5) clear when input signal low, and ACKINT1(7-5) bit are already set.
• REGSTATUS(3-0) clear when input signal is low.
• ACKINT2(7-0) clear when REGSTATUS(7-0) is clear.

The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not usually written to by the CPU because the TPS65014 internally sets/clears these registers:

• ACKINT1(7:0): Bit is set when the corresponding CHGSTATUS set bit is read through I²C.
• ACKINT1(7:0): Bit is cleared when the corresponding CHGSTATUS set bit clears.
• ACKINT2(7:0): Bit is set when the corresponding REGSTATUS set bit is read through I²C.
• ACKINT2(7:0): Bit is cleared when the corresponding REGSTATUS set bit clears.
• ACKINT1(7:0): A bit set masks the corresponding CHGSTATUS bit from INT.
• ACKINT2(7:0): A bit set masks the corresponding REGSTATUS bit from INT.

The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:

• MASK1(7:0): A bit set in this register masks CHGSTATUS from INT.
• MASK2(7:0): A bit set in this register masks REGSTATUS from INT.
• MASK3(7:4): A bit set in this register detects a rising edge on GPIO.
• MASK3(7:4): A bit cleared in this register detects a falling edge on GPIO.
• MASK3(3:0): A bit set in this register clears GPIO Detect signal from INT.

GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read from DEFGPIO<7:4>, which GPIO is set to input or output. This information together with the information on which edge the interrupt was generated (the CPU either knows this or can read it from MASK3<7:4>) determines whether the CPU is looking for a 0 or a 1 in DEFGPIO<3:0>. A GPIO interrupt is blocked from the INT pin by setting the relevant MASK3<3:0> bit; this must be done by the CPU, there is no auto-acknowledge for the GPIO interrupts.

7.3.9 Serial Interface

The serial interface is compatible with the standard and fast mode I²C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as V_CC remains above 2 V. The TPS65014 has a 7-bit address with the LSB set by the IFLSB pin; this allows the connection of two devices with the same address to the same bus. The 6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65014 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65014 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65014 device must leave the data line high to enable the master to generate the stop condition.

The I²C interface accepts data as soon as the voltage at V_CC is higher than the undervoltage lockout threshold and one power rail of the converter (main, core, or one of the LDOs) is operating. Therefore, the I²C interface is not operating after applying the battery voltage as the device automatically enters the WAIT mode with all rails off.

When the device is in WAIT mode, the I²C registers are reset to their default values if all voltage rails are off. If the device is in WAIT mode and one power rail is left on, the I²C interface is operating and the registers are not reset after leaving the WAIT mode.

Figure 31. Bit Transfer on the Serial Interface

Figure 32. START and STOP Conditions

NOTE:

SLAVE = TPS65014

Figure 33. Serial Interface WRITE to TPS65014 Device

NOTE:

SLAVE = TPS65014

Figure 34. Serial Interface READ From TPS65014: Protocol A

NOTE:

SLAVE = TPS65014

Figure 35. Serial Interface READ From TPS65014: Protocol B

Figure 36. Serial Interface Timing Diagram

7.4.1 Power Save Mode Operation

As the load current decreases, the converter enters the power-save mode operation. During power-save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency.

To optimize the converter efficiency at light load, the average current is monitored; if in PWM mode, the inductor current remains below a certain threshold, and then power-save mode is entered. The typical threshold can be calculated as in Equation 2:

Equation 2.

During the power-save mode, the output voltage is monitored with the comparator by the thresholds comp low and comp high. As the output voltage falls below the comp low threshold, set to typically 0.8% above the nominal V_out, the P-channel switch turns on. The converter then runs at 50% of the nominal switching frequency. If the load is below the delivered current, then the output voltage rises until the comp high threshold is reached, typically 1.6% above the nominal V_out. At this point, all switching activity ceases, thus reducing the quiescent current to a minimum until the output voltage has dropped below comp low again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the nominal output voltage threshold (comp low 2 threshold), whereupon power-save mode is exited, and the converter returns to PWM mode.

These control methods reduce the quiescent current typically to 12 µA per converter and the switching frequency to a minimum, achieving the highest converter efficiency. Setting the comparator thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning achieving lower absolute voltage drops during heavy load transient changes. This allows the converters to operate with a small output capacitor of just 10 µF for the core and 22 µF for the main output and still have a low absolute voltage drop during heavy load transient changes. See Figure 37 for detailed operation of the power-save mode. The power-save mode can be disabled through the I²C interface to force the converters to stay in fixed frequency PWM mode.

Figure 37. Power-Save Mode Thresholds and Dynamic Voltage Positioning

7.4.2 Sleep Mode

The TPS65014 charger enters the low-power sleep mode if both input sources are removed from the circuit. This feature prevents draining the battery during the absence of input power.

7.5.1 CHGSTATUS Register (offset = 01h) (reset: 00h)

Bits 1-4 may be reset through the serial interface in order to force a reset of the charger. Any attempt to write to Bit 0 and Bits 5-7 is ignored. A 1 in <7:0> sets the INT pin active unless the corresponding bit in the MASK register is set.

7.5.2 REGSTATUS Register (offset = 02h) (reset: 00h)

A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.

7.5.3 MASK1 Register (offset = 03h) (reset: FFh)

The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS<7:0> positions indicated at the INT pin. Default is to mask all.

7.5.4 MASK2 Register (offset = 04h) (reset: FFh)

The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS<7:0> positions indicated at the INT pin. Default is to mask all.

7.5.5 ACKINT1 Register (offset = 05h) (reset: 00h)

The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding CHGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it will remain low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access the ACKINT1 register.

7.5.6 ACKINT2 Register (offset: 06h) (reset: 00h)

The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding REGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it will remain low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding interrupt condition in REGSTATUS is removed. The application processor should not normally need to access the ACKINT2 register.

7.5.7 CHGCONFIG Register (offset: 07h) (reset: 1Bh)

The CHGCONFIG register is used to configure the charger.

7.5.8 LED1_ON Register (offset: 08h) (reset: 00h)

The LED1_ON and LED1_PER registers can be used to take control of the PG open-drain output normally controlled by the charger.

7.5.9 LED1_PER Register (offset: 09h) (reset: 00h)

7.5.10 LED2_ON Register (offset: 0Ah) (reset: 00h)

The LED2_ON and LED2_PER registers are used to control the LED2 open-drain output.

7.5.11 LED2_PER (offset: 0Bh) (reset: 00h)

7.5.12 VDCDC1 Register (offset: 0Ch) (reset: 32h/33h)

The VDCDC1 register is used to program the VMAIN switching converter.

7.5.13 VDCDC2 Register (offset: 0Dh) (reset: 60h/70h)

The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8 steps between 0.85 V and 1.8 V. The default value is governed by the DEFCORE pin; DEFCORE=0 sets an output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.8 V.

7.5.14 VREGS1 Register (offset: 0Eh) (reset: 88h)

The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low power mode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.

7.5.15 MASK3 Register (offset: 0Fh) (reset: 00h)

The MASK3 register must be considered when any of the GPIO pins are programmed as inputs.

7.5.16 DEFGPIO Register (offset = 10h) (reset: 00h)

The DEFGPIO register is used to define the GPIO pins to be either input or output.