SLVS517B August   2004  – September 2015 TPS65013

PRODUCTION DATA.  

1. 1 Features
2. 2 Applications
3. 3 Description
4. 4 Revision History
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 Battery Charger Electrical Characteristics
   7. 6.7 Serial Interface Timing Requirements
   8. 6.8 Dissipation Ratings
   9. 6.9 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Battery Charger
         1. 7.3.1.1 Autonomous Power Source Selection
         2. 7.3.1.2 Temperature Qualification
         3. 7.3.1.3 Battery Preconditioning
         4. 7.3.1.4 Battery Charge Current
         5. 7.3.1.5 Battery Voltage Regulation
         6. 7.3.1.6 Charge Termination and Recharge
         7. 7.3.1.7 Sleep Mode
         8. 7.3.1.8 PG Output
         9. 7.3.1.9 Thermal Considerations for Setting Charge Current
      2. 7.3.2 Step-Down Converters, VMAIN and VCORE
         1. 7.3.2.1 Power-Save Mode Operation
         2. 7.3.2.2 Forced PWM
         3. 7.3.2.3 Dynamic Voltage Positioning
         4. 7.3.2.4 Soft Start
         5. 7.3.2.5 100% Duty Cycle Low-Dropout Operation
         6. 7.3.2.6 Active Discharge When Disabled
         7. 7.3.2.7 Power-Good Monitoring
         8. 7.3.2.8 Overtemperature Shutdown
      3. 7.3.3 Low-Dropout Voltage Regulators
         1. 7.3.3.1 Power-Good Monitoring
         2. 7.3.3.2 Enable and Sequencing
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Power-Up Sequencing
      6. 7.3.6 System Reset and Control Signals
      7. 7.3.7 Vibrator Driver
   4. 7.4 Device Functional Modes
      1. 7.4.1 TPS65013 Power States Description
         1. 7.4.1.1 State 1: No Power
         2. 7.4.1.2 State 2: ON
         3. 7.4.1.3 State 3: Low-Power Mode
         4. 7.4.1.4 State 4: Shutdown
   5. 7.5 Programming
      1. 7.5.1 LED2 Output
      2. 7.5.2 Interrupt Management
      3. 7.5.3 Serial Interface
   6. 7.6 Register Maps
      1. 7.6.1  CHGSTATUS Register (Address: 01h—Reset: 00h)
      2. 7.6.2  REGSTATUS Register (Address: 02h—Reset: 00h)
      3. 7.6.3  MASK1 Register (Address: 03h—Reset: FFh)
      4. 7.6.4  MASK2 Register (Address: 04h—Reset: FFh)
      5. 7.6.5  ACKINT1 Register (Address: 05h—Reset: 00h)
      6. 7.6.6  ACKINT2 Register (Address: 06h—Reset: 00h)
      7. 7.6.7  CHGCONFIG Register Address: 07h—Reset: 1Bh
      8. 7.6.8  LED1_ON Register (Address: 08h—Reset: 00h)
      9. 7.6.9  LED1_PER Register (Address: 09h—Reset: 00h)
      10. 7.6.10 LED2_ON Register (Address: 0Ah—Reset: 00h)
      11. 7.6.11 LED2_PER (Register Address: 0Bh—Reset: 00h)
      12. 7.6.12 VDCDC1 Register (Address: 0Ch—Reset: 32h/33h)
      13. 7.6.13 VDCDC2 Register (Address: 0Dh—Reset: 48h/78h)
      14. 7.6.14 VREGS1 Register (Address: 0Eh—Reset: 88h)
      15. 7.6.15 MASK3 Register (Address: 0Fh—Reset: 00h)
      16. 7.6.16 DEFGPIO Register Address: (10h—Reset: 00h)
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
         1. 8.2.2.1 Inductor Selection for the Main and the Core Converter
         2. 8.2.2.2 Output Capacitor Selection
         3. 8.2.2.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
   3. 8.3 System Example
9. 9 Power Supply Recommendations
   1. 9.1 LDO1 Output Voltage Adjustment
10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
12. 12Mechanical, Packaging, and Orderable Information