9.3.1 Step-Down Converter

TI intends the step-down converter to maximize the flexibility in the equipment. The output voltage is selectable with a resistor network on the output. Figure 15 shows the required connections.

Figure 15. DCDC Block Diagram and Output Voltage Setting

The output voltage of the DC-DC converter is set by Equation 1:

Equation 1.

The combined resistance of R_DC1 and R_DC2 should be less than 1 MΩ.

Fixed output voltages and additional current limit options are also possible. Contact TI for further information.

The step-down converter has two modes of operation to maximize efficiency at different load conditions. At moderate to heavy load currents, the device operates in a fixed-frequency pulse width modulation (PWM) mode that results in small output ripple and high efficiency. Pulling the MODE pin to a DC-high level results in PWM mode over the load range.

At light-load currents, the device operates in a pulsed-frequency modulation (PFM) mode to improve efficiency. The transition to this mode occurs when the inductor current through the low-side FET becomes zero, indicating discontinuous conduction. PFM mode also results in the output voltage increasing by 1% from its nominally set value. TI intends this voltage positioning to minimize the voltage undershoot of a load step from light to heavy loads, as when a processor moves from sleep to active modes, and the voltage overshoot at load throw-off. Figure 16 shows the voltage positioning behavior for a light to heavy load step.

Figure 16. PFM Voltage Positioning

Pulling the MODE pin to DC ground results in an automatic transition between PFM and PWM modes to maximize efficiency.

The DC-DC converter output automatically discharges to ground through an internal 450-Ω load when EN_DCDC goes low or when the UVLO condition is met.

9.3.2 Soft Start

The step-down converter has an internal soft start circuit that limits the inrush current during start-up. During a soft start, the output voltage ramp up is controlled as Figure 17 shows.

Figure 17. Soft Start

9.3.3 Linear Regulators

TI designed the two linear drop-out regulators (LDOs) in the TPS65000 and TPS65001 to provide flexibility in system design. Each LDO has a separate voltage input and enable signal. The input can be tied to the output of the step-down converter or the output of another voltage source. Each LDO output discharge to ground automatically when EN_LDOx goes low.

A resistor network is required to set the output voltage of the LDOs. Fixed-voltage output versions are also available. Contact TI sales representative for more information.

The LDOs are general-purpose devices that can handle inputs from 6 V to 1.6 V, making them suitable for directly connecting to the battery. Figure 18 illustrates the connections for LDO1. The same architecture applies to LDO2.

Figure 18. LDO Block Diagram and Output Voltage Setting

The output voltages of the LDOs are set by Equation 2:

Equation 2.

The combined resistance of R_{LDO1_1} and R_{LDO1_2} should be less than 1 MΩ.

9.3.4 Oscillator and Spread Spectrum Clock Generation

The TPS6500x contains an internal oscillator running at a typical frequency of 2.25 MHz. This frequency is the fundamental switching frequency of the step-down converter when running in PWM mode. An additional circuit in the oscillator block implements spread spectrum clocking, which modulates the main-switching frequency when the device is in PWM mode. This spread spectrum oscillation reduces the power that may cause EMI. When viewed in the frequency domain, the SSC spreads out the frequency that may introduce interference while simultaneously reducing the power. Because the frequency is continually shifting, the amount of time the switcher spends at any single frequency is reduced. This reduction in time indicates that the receiver that may sense the interference has less time to integrate the interference.

Different spin versions of SSC settings are also feasible. Contact a TI sales representative for more information.

Figure 19. SSC On/Off Comparison from 1.5 MHz to 150 MHz

Figure 20. Zoom In of SSC On/Off Comparison from 1.5 MHz to 3.5 MHz

Figure 19 to Figure 20 shows the advantage of SSC with the frequency spectrum centering on the nominal frequency 2.25 MHz. The blue spectrum is the result of the spread change. The figures show the harmonic spectrum is attenuated 10 dB comparing to the same device without SSC.

9.3.5 Power Good

The open drain PG output indicates the condition of the step-down converter and each LDO. This output is combined, with the outputs being compared when the appropriate enable signal is high. The pin is pulled low when all enabled outputs are greater than 90% of the target voltage and Hi-Z when an enabled output is less than 90% of its intended value or when all the enable signals are pulled low.

Figure 21. Power Good Functionality

9.3.6 Supply Voltage Supervisor (SVS) [TPS65001 and TPS650061 Only]

The SVS has fourinputs and one output. The RST pin is an active-low high-impedance output. The MR pin is an active-low input that suitable for connecting to a push-button circuit for manual reset generation. The RSTSNS pin is an analog-input pin for voltage comparison. The TRST pin is connected to an external capacitor, allowing the reset timing to be set in the application. The VINDCDC pin is the main-supply input for the control circuits and the switch-mode converter.

Figure 22. SVS Block Diagram

Each input can individually trigger RST to go active. Table 1 outlines the paths to activate the reset.

The RSTSNS pin must be tied to VINDCDC if the reset functionality is not required from this pin. This action causes the reset to activate only when VINDCDC is rising from 0 V or when VINDCDC drops below UVLO. The RSTSNS pin must connect to an external RC network to set the deglitch timing for triggering a reset when VINDCDC is below the UVLO threshold. The reset threshold voltage is given by Equation 3:

Equation 3.

The RST recovery timing is set by the capacitor on the TRST pin. A 2-μA current is enabled when the reset condition is met, charging the capacitor. The TRST voltage is monitored internally and the reset ends when the voltage reaches 0.6 V. The capacitor value to reset time can be computed with Equation 4:

Equation 4.

The value t_RST is the time from the end of condition that activated RST until RST returns to its Hi-Z state. The TRST pin would be internally discharged to ground when the reset condition is true or after t_RST.

Figure 23. RST Recovery Timing