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SLVS810C June 2009 – September 2015 TPS65000 , TPS650001 , TPS650003 , TPS650006 , TPS65001 , TPS650061

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RTE|16
- MPQF149D

散熱焊盤機械數據 (封裝 | 引腳)

RTE|16
- QFND525B

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input voltage range	On all pins except AGND, PGND, EN_DCDC, VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC pins with respect to AGND	–0.3	7	V
Input voltage range	On EN_DCDC with respect to AGND	–0.3	V_IN + 0.3, ≤ 7	V
Output voltage range	On VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC	–0.3	3.6	V
Current	VINDCDC, SW, PGND,		1800	mA
	VINLDO1/2, VLDO1/2, AGND		800	mA
	At all other pins		1	mA
Continuous total power dissipation		See Dissipation Ratings
Operating free-air temperature, T_A		–40	85	°C
Maximum junction temperature, T_J			125	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2500	V
		Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±2000
		Machine model (MM)	±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
L1	SW pin inductor	1.5	2.2	3.3	μH
C_I	Input capacitor at VINDCDC	10			μF
C_I	Input capacitor at VINLDO1/2	2.2			μF
C_O	Output capacitor for DCDC	10		22	μF
C_O	Output capacitor for LDO1/2	2.2			μF
I_O	DC-DC converter output current			600	mA
	DC-DC converter output current (TPS650061 ONLY)			1000	mA
	LDO1 output current			300	mA
	LDO2 output current			300	mA
T_A	Operating ambient temperature	–40		85	°C

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS6500x		UNIT
		RTE (WQFN)	RUK (WQFN)
		16 PINS	20 PINS
R_θJA	Junction-to-ambient thermal resistance	44.7	46.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	41.7	51	°C/W
R_θJB	Junction-to-board thermal resistance	16	17.8	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	0.7	°C/W
ψ_JB	Junction-to-board characterization parameter	16	17.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4.4	4.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Over full operating ambient temperature range, typical values are at T_A = 25°C. Unless otherwise noted, specifications apply for condition V_IN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, C_OUT = 10 μF, C_IN = 4.7 μF, (see the Typical Application section).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OPERATING VOLTAGE
V_IN	Input voltage for VINDCDC of DC-DC converter		2.3		6	V
	Input voltage for LDO1 (VINLDO1)	See ⁽¹⁾	1.6		6
	Input voltage for LDO2 (VINLDO2)	See ⁽¹⁾	1.6		6
UVLO	Internal undervoltage lockout threshold	V_CC falling	1.72	1.77	1.82	V
UVLO	Internal undervoltage lockout hysteresis			160		mV
SUPPLY CURRENT TPS65000
I_Q	Operating quiescent current	MODE low, EN_DCDC high, EN_LDO1/2 low, I_OUT = 0 mA and no switching		23	32	μA
		MODE low, EN_DCDC low, EN_LDO1/2 high, I_OUT = 0 mA I_OUT = 0 mA and no switching⁽²⁾		50	57	μA
		EN_DCDC high, MODE high, EN_LDO1/2 low, I_OUT = 0 mA		4		mA
I_SD	Shutdown Current	EN_DCDC low EN_LDO1 and EN_LDO2 low		0.16	2.2	μA
SUPPLY CURRENT TPS65001
I_Q	Operating quiescent current	MODE low, EN_DCDC high, EN_LDO1/2 low, I_OUT = 0 mA and no switching		24	37	μA
		MODE low, EN_DCDC low, EN_LDO1/2 high, I_OUT = 0 mA I_OUT = 0 mA and no switching⁽²⁾		55	62	μA
		EN_DCDC high, MODE high, EN_LDO1/2 low, I_OUT = 0 mA		4		mA
I_SD	Shutdown Current	EN_DCDC low EN_LDO1 and EN_LDO2 low		11	17	μA
DIGITAL PINS (EN_DCDC, EN_LDO1, EN_LDO2, MODE, PG, MR, RST)
V_IH	High-level input voltage		1.2			V
V_IL	Low-level input voltage				0.4	V
V_OL	Low-level output voltage	PG and RST pins only, I_O = -100 μA			0.4	V
I_lkg	Input leakage current	MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to GND or VINDCDC		0.01	0.1	μA
OSCILLATOR
f_SW	Oscillator frequency		1.722	2.25	2.847	MHz
STEP DOWN CONVERTER POWER SWITCH
R_DS(on)	High-side MOSFET ON-resistance	VINDCDC = V_GS = 3.6 V		240	480	mΩ
R_DS(on)	Low-side MOSFET ON-resistance	VINDCDC = V_GS = 3.6 V		185	380	mΩ
I_O	DC-output current	2.3 V ≤ VINDCDC ≤ 2.5 V			300	mA
I_O	DC-output current	2.5 V ≤ VINDCDC ≤ 6 V			600	mA
I_O	DC-output current (TPS650061 ONLY)	2.7 V ≤ VINDCDC ≤ 6 V			1000	mA
I_LIMF	Forward current limit PMOS and NMOS	2.3 V ≤ VINDCDC ≤ 6 V	800	1000	1400	mA
I_LIMF	Forward current limit PMOS and NMOS (TPS650061 ONLY)	2.7 V ≤ VINDCDC ≤ 6 V	1200	1500	1680	mA
T_SD	Thermal shutdown	Increasing junction temperature		150		°C
T_SD	Thermal shutdown hysteresis	Decreasing junction temperature		30		°C
STEP DOWN CONVERTER OUTPUT VOLTAGE
VDCDC	Adjustable output voltage range, DCDC		0.6	VINDCDC		V
	FB_DCDC pin current				0.1	μA
V_ref	Internal reference voltage		0.594	0.6	0.606	V
VDCDC	Output Voltage Accuracy (PWM Mode)⁽³⁾	MODE = high, 2.3 ≤ VINDCDC ≤ 6 V	–1.5%	0%	1.5%
VDCDC	Output Voltage Accuracy (PFM mode) ⁽⁴⁾	MODE low 1% voltage positioning active		1%
	Load regulation (PWM mode)	MODE high		0.5%		A
R_DIS	Internal discharge resistance at SW	EN_DCDC low		450		Ω
LOW DROP OUT REGULATORS
V_I	Input voltage for LDOx (VINLDOx)		1.6		6	V
V_O	Adjustable output voltage, LDOx (VLDOx)⁽⁵⁾		0.73	VINLDOx – V_DO		V
I_O	Continuous Pass FET Current				300	mA
I_SC	Short circuit current limit	2.3 V ≤ VINLDOx	340		700	mA
I_SC	Short circuit current limit	VINLDOx < 2.3V	210		700	mA
	FB_LDOx pin current				0.1	μA
	FB_LDOx voltage	Adjustable V_OUT mode only		0.5		V
V_DO	Dropout Voltage ⁽⁶⁾	VINLDOx ≥ 2.3 V, I_OUT = 250 mA			370	mV
V_DO	Dropout Voltage ⁽⁶⁾	VINLDOx < 2.3V I_OUT = 175 mA			370	mV
LOW DROP OUT REGULATORS (continued)
	Output Voltage Accuracy ⁽⁷⁾	I_O = 1 mA to 300 mA, VINLDOx = 2.3 V – 6 V, VLDOx = 1.2 V	–3.5%		3.5%
	Output Voltage Accuracy ⁽⁷⁾	I_O = 1mA to 175 mA VINLDOx = 1.6 V – 6 V, VLDOx = 1.2 V	–3.5%		3.5%
	Load regulation	I_O = 1mA to 300 mA VINLDOx = 3.6 V VLDOx = 1.2 V	–1.5%		1.5%
	Line regulation	VINLDOx = 1.6 V – 6 V VLDOx = 1.2 V at I_O = 1 mA	–0.5%		0.5%
PSRR	Power Supply Rejection Ratio	f_NOISE ≤ 10 kHz, C_OUT ≥ 2.2 μF, V_IN = 2.3 V, V_OUT = 1.3 V I_OUT = 10 mA		40		dB
R_DIS	Internal discharge resistance at VLDOx	EN_LDOx low		450		Ω
T_SD	Thermal shutdown	Increasing temperature		150		°C
	Thermal shutdown hysteresis	Decreasing temperature		30		°C
SUPPLY VOLTAGE SUPERVISOR
V_IN	Input voltage for RSTSNS pin		0		6	V
t_MRDEGLITCH	MR Deglitch time			1		ms
V_IH	Input high voltage	MR pin only	1.2		6	V
V_IL	Input low voltage	MR pin only	0		0.4	V
I_lkg	High-input leakage current	RST pin		0.01	0.1	μA
V_OL	Output low voltage	RST pin only, I_O = –100 μA			0.4	V
I_TRST	Reset timer capacitor current		1.6	2	2.2	μA
	Reset voltage trip voltage	Voltage rising (Reset time begins)	0.58	0.6	0.63	V
	Reset voltage trip hysteresis	Voltage falling (RST pulled low)		–5%

(1) The design principle lets only VINDCDC be the highest supply in the system if different voltage input supplies separately to DC-DC converter and LDOs, meaning VINDCDC ≥ VINLDO1, VINDCDC ≥ VINLDO2.

(2) The max quiescent current of enabling LDOs is 8 μA higher for TPS650001, TPS650003, TPS650006, and TPS650061.

(3) For VINDCDC = VDCDC + 1 V

(4) In PFM Mode, the internal reference voltage is typ 1.01 × V_REF.

(5) Maximum output voltage VLDOx = 3.6 V.

(6) V_DO = VINLDOx – VLDOx where VINLDOx = VLDOx (nominal) – 100 mV

(7) Output voltage specification does not include tolerance of external programming resistors.

8.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	UNIT
STEP DOWN CONVERTER OUTPUT VOLTAGE
t_Start	Start-up time	EN_DCDC to start of switching (10%)	250	μs
t_Ramp	VDCDC ramp-up time	VDCDC ramp from 10% to 90%	250	μs
LOW DROP OUT REGULATORS
t_RAMP	VLDOx Ramp Time	VLDOx ramp from 10% to 90%	200	μs