ZHCSKE6C July 2019 – February 2020 TPS63810 , TPS63811
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 器件比較表
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Control Scheme
- 8.3.2 Control Scheme
- 8.3.3 Power-Save Mode Operation (PSM)
- 8.3.4 Forced-PWM Operation (FPWM)
- 8.3.5 Ramp-PWM Operation (RPWM)
- 8.3.6 Device Enable (EN)
- 8.3.7 Undervoltage Lockout (UVLO)
- 8.3.8 Soft Start
- 8.3.9 Output Voltage Control
- 8.3.10 Protection Functions
- 8.3.11 Power Good
- 8.3.12 Load Disconnect
- 8.3.13 Output Discharge
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Map
- 8.6.1
Register Description
- 8.6.1.1 Register Map
- 8.6.1.2 Register CONTROL (Slave address: 0b1110101; Register address: 0x01; Default: 0x00 or 0x20)
- 8.6.1.3 Register STATUS (Slave address: 0b1110101; Register address: 0x02; Default: 0x00)
- 8.6.1.4 Register DEVID (Slave address: 0b1110101; Register address: 0x03; Default: 0x04)
- 8.6.1.5 Register VOUT1 (Slave address: 0b1110101; Register address: 0x04; Default: 0x3C)
- 8.6.1.6 Register VOUT2 (Slave address: 0b1110101; Register address: 0x05; Default: 0x42)
- 8.6.1
Register Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.5.3 I2C Update Sequence
A single update requires the following:
- A start condition
- A valid I2C slave address
- A register address
- A data byte
To acknowledge the receipt of each byte, the device pulls the SDA line low during the high period of a single clock pulse. The device performs an update on the falling edge of the acknowledge signal that follows the last byte.
WHITESPACE
Figure 24. “Write” Data Transfer Format in Standard, Fast, and Fast-Plus Modes 
Figure 25. “Read” Data Transfer Format in Standard, Fast, and Fast-Plus Modes