ZHCSO49C May 2021 – March 2023 TPS629210-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
- 8.3.2 Adjustable VO Operation (External Voltage Divider)
- 8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
- 8.3.4 Smart Enable with Precise Threshold
- 8.3.5 Power Good (PG)
- 8.3.6 Output Discharge Function
- 8.3.7 Undervoltage Lockout (UVLO)
- 8.3.8 Current Limit and Short Circuit Protection
- 8.3.9 Thermal Shutdown
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
9.3.1 Powering Multiple Loads
In applications where the TPS629210-Q1 is used to power multiple load circuits, it is possible that the total capacitance on the output is very large. To properly regulate the output voltage, there must be an appropriate AC signal level on the VOS pin. Tantalum capacitors have a large enough ESR to keep output voltage ripple sufficiently high on the VOS pin. With low-ESR ceramic capacitors, the output voltage ripple can get very low, so it is not recommended to use a large capacitance directly on the output of the device. If there are several load circuits with their associated input capacitor on a PCB, these loads are typically distributed across the board. This adds enough trace resistance (Rtrace) to keep a large enough AC signal on the VOS pin for proper regulation.
The minimum total trace resistance on the distributed load is 10 mΩ. The total capacitance n × CIN in Figure 9-83 was 32 × 47 μF of ceramic X7R capacitors.
Figure 9-83 Multiple Loads Example