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ZHCSS16 april 2023 TPS62902-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RYT|9
- MPSS145A

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcss16_oa

7.5 Electrical Characteristics

V_I = 3 V to 18 V, T_J = -40C °C to +165°C, Typical values at V_I = 12 V and T_A = 25 °C unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
I_Q	Operating Quiescent Current (Power Save Mode)	Iout = 0 mA device not switching		4		μA
I_Q;PWM	Operating Quiescent Current (PWM Mode)	VIN= 12V, VOUT=1.2V; Iout = 0 mA, device switching		8		mA
I_SD	Shutdown current into VIN pin	EN = 0 V, T_J = –40 °C to 150°C		0.27	3.5	μA
V_UVLO	Under Voltage Lock-Out	V_IN rising, T_J = –40 °C to 150°C	2.85	2.925	3.0	V
V_UVLO	Under Voltage Lock-Out	V_IN falling	2.71	2.79	2.87	V
V_UVLO	Under Voltage Lock-Out Hysteresis			130		mV
CONTROL & INTERFACE
I_LKG	EN Input leakage current	EN = 5 V		10	310	nA
V_IH;MODE	High-Level Input Voltage at MODE/S-CONF Pin		1.0			V
V_IL;MODE	Low-Level Input Voltage at MODE/S-CONF Pin				0.15	V
T_SD	Thermal Shutdown Threshold	T_J rising	168	175	185	°C
T_SD	Thermal Shutdown Hysteresis	T_J falling		12.5		°C
V_IH	High-level input voltage at EN-Pin		0.97	1.0	1.03	V
V_IL	Low-level input voltage at EN-Pin		0.820	0.850	0.880	V
V_PG	Power good fthreshold	V_FB rising, referenced to V_FB nominal	93%	96%	99%
V_PG	Power good fthreshold	V_FB falling, referenced to V_FB nominal	88%	92%	96%
V_{PG_HYS}	Power good threshold hysteresis		1.5%	3.5%	6%
V_PG,OL	Low-level output voltage at PG pin	I_SINK = 1 mA			0.4	V
I_PG,LKG	Input leakage current into PG pin	V_PG = 5 V, T_J = –40 °C to 150 °C		25	550	nA
t_PG,DLY	Power good delay time	V_FB rising and falling		32		μs
C_SET	Maximum Capacitance connected to VSET pin				30	pF
POWER SWITCHES
I_LKG;SW	Leakage current into SW-Pin	EN = 0 V, V_SW = V_OS = 5.5 V, T_J up to 150°C		2	7	μA
R_DS;ON	High-side FET on resistance	V_IN > 4 V, I_SW = 500 mA		62	111	mΩ
R_DS;ON	Low-side FET on resistance	V_IN > 4 V, I_SW = 500 mA		22	41	mΩ
I_LIM	High-side FET current limit		2.7	3.2	3.9	A
I_LIM	Low-side FET current limit		2.5	3	3.5	A
I_LIM;SINK	Low-side FET sink current limit		1.3	1.7	2.5	A
f_SW	Switching frequency	2.5-MHz selection		2.5		MHz
T_ON(MIN)	Minimum On-time			30		ns
f_SW	Switching frequency	1.0-MHz selection		1.0		MHz
OUTPUT
V_O	Output Voltage Regulation	VSET Configuration selected, T_J = 25°C	–1%		+1%
V_O	Output Voltage Regulation	VSET Configuration selected	–1.5%		+1.5%
V_FB	Feedback Regulation Voltage	Adjustable Configuration selected		0.6		V
V_FB	Feedback Voltage Regulation	FB-Option selected. T_J= 25 °C.	–0.6%		+0.6%
V_FB	Feedback Voltage Regulation	FB-Option selected	–1.25%		+1.25%
I_FB	Input leakage current into FB pin	Adjustable configuration, VFB = 0.6 V		1	70	nA
T_delay	Start-up delay time	I_O = 0 mA, time from EN=HIGH until start switching, Adjustable Configuration selected		600	1400	μs
T_delay	Start-up delay time	I_O = 0 mA, time from EN=HIGH until start switching, VSET Configuration selected. The typical value is based on the first option of VSET configuration.		650	1850	μs
T_SS	Soft-Start time	I_O = 0 mA after T_delay, from 1^st switching pulse until target V_O ,Css=Open		150		μs
I_SS	SS/TR source current		2.25	2.5	2.75	μA
V_FB/V_SS/TR	Tracking Gain, Adjustable Configuration			0.75
V_FB/V_SS/TR	Tracking Gain tolerance			±8		mV
R_DISCH	Active Discharge Resistance	Discharge = ON - Option Selected, EN = LOW		7.5	30	?