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ZHCSHY6I March 2018 – March 2024 TPS62824 , TPS62824A , TPS62825 , TPS62825A , TPS62826 , TPS62826A , TPS62827 , TPS62827A

PRODUCTION DATA

封裝選項

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DMQ|6
- MPSS077D

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

T_J = -40 °C to 125 °C, and V_IN = 2.4 V to 5.5 V. Typical values are at T_J = 25 °C and V_IN = 5 V , unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
I_Q	Quiescent current	EN = High, no load, device not switching		4	10	μA
I_Q	Quiescent current	EN = High, no load, FPWM devices		8		mA
I_SD	Shutdown current	EN = Low, T_J = -40 ℃ to 85 ℃		0.05	0.5	μA
V_UVLO	Under voltage lock out threshold	V_IN falling	2.1	2.2	2.3	V
V_UVLO	Under voltage lock out hysteresis	V_IN rising		160		mV
T_JSD	Thermal shutdown threshold	T_J rising		150		°C
T_JSD	Thermal shutdown hysteresis	T_J falling		20		°C
LOGIC INTERFACE EN
V_IH	High-level threshold voltage		1.0			V
V_IL	Low-level threshold voltage				0.4	V
I_EN,LKG	Input leakage current into EN pin	EN = High		0.01	0.1	μA
SOFT START, POWER GOOD
t_SS	Soft start time	Time from EN high to 95% of V_OUT nominal, TPS62827		1.75		ms
t_SS	Soft start time	Time from EN high to 95% of V_OUT nominal, TPS62824x/5x/6x/7A		1.25		ms
V_PG	Power good lower threshold	V_PG rising, V_FB referenced to V_FB nominal	94	96	98	%
	Power good lower threshold	V_PG falling, V_FB referenced to V_FB nominal	90	92	94	%
	Power good upper threshold	V_PG rising, V_FB referenced to V_FB nominal	108	110	112	%
	Power good upper threshold	V_PG falling, V_FB referenced to V_FB nominal	103	105	107	%
V_PG,OL	Low-level output voltage	I_sink = 1 mA			0.4	V
I_PG,LKG	Input leakage current into PG pin	V_PG = 5.0 V		0.01	0.1	μA
t_PG,DLY	Power good deglitch delay	PG rising edge		100		μs
t_PG,DLY	Power good deglitch delay	PG falling edge		20		μs
OUTPUT
V_OUT	Output voltage accuracy	TPS6282533, PWM mode	3.267	3.3	3.333	V
V_OUT	Output voltage accuracy	TPS6282x18, PWM mode	1.78	1.8	1.82	V
V_FB	Feedback regulation voltage	PWM mode	594	600	606	mV
I_FB,LKG	Feedback input leakage current for adjustable output voltage	V_FB = 0.6 V		0.01	0.05	μA
R_FB	Internal resistor divider connected to FB pin, for fixed output votlage	TPS6282518, TPS6282618, TPS6282533		7.5		M?
I_DIS	Output discharge current	V_SW = 0.4V; EN = LOW	75	400		mA
	Load regulation	I_OUT= 0.5 A to 3 A, V_OUT = 1.8 V		0.1		%/A
POWER SWITCH
R_DS(on)	High-side FET on-resistance			26		m?
R_DS(on)	Low-side FET on-resistance			25		m?
I_LIM	High-side FET switch current limit, DC	TPS62824A	1.7	2.1	2.4	A
		TPS62825x	2.74	3.3	3.9	A
		TPS62826x	3.7	4.3	5.0	A
		TPS62827x	4.8	5.6	6.4	A
I_LIM	Low-side FET negative current limit, DC	TPS62824A/5A/6A/7A		–1.6		A
f_SW	PWM switching frequency	I_OUT= 1 A, V_OUT = 1.8 V		2.2		MHz