ZHCSNK8 March 2021 TPS62810M , TPS62811M , TPS62812M , TPS62813M
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| SUPPLY | |||||||
| IQ | Operating quiescent current | EN = high, IOUT = 0 mA, device not switching, TJ = 125°C |
21 | μA | |||
| IQ | Operating quiescent current | EN = high, IOUT = 0 mA, device not switching | 15 | 30 | μA | ||
| ISD | Shutdown current | EN = 0 V, at TJ = 125 °C | 18 | μA | |||
| ISD | Shutdown current | EN = 0 V, nominal value at TJ = 25 °C, max value at TJ = 150°C |
1.5 | 26 | μA | ||
| VUVLO | Undervoltage lockout threshold | Rising input voltage | 2.5 | 2.6 | 2.75 | V | |
| Falling input voltage | 2.25 | 2.5 | 2.6 | V | |||
| TSD | Thermal shutdown temperature | Rising junction temperature | 170 | °C | |||
| Thermal shutdown hysteresis | 15 | ||||||
| CONTROL (EN, SS/TR, PG, MODE) | |||||||
| VIH | High level input voltage for MODE pin | 1.1 | V | ||||
| VIL | Low level input voltage for MODE pin | 0.3 | V | ||||
| fSYNC | Frequency range on MODE pin for synchronization | Requires a resistor from COMP/FSET to GND, see the Application and Implementation section | 1.8 | 4 | MHz | ||
| Duty cycle of synchronization signal at MODE pin | 40% | 50% | 60% | ||||
| Time to lock to external frequency | 50 | μs | |||||
| VIH | Input threshold voltage for EN pin; rising edge | 1.06 | 1.1 | 1.15 | V | ||
| VIL | Input threshold voltage for EN pin; falling edge | 0.96 | 1.0 | 1.05 | V | ||
| ILKG | Input leakage current for EN, MODE/SYNC | VIH = VIN or VIL = GND | 150 | nA | |||
| Resistance from COMP/FSET to GND for logic low | Internal frequency setting with f = 2.25 MHz | 0 | 2.5 | kΩ | |||
| Voltage on COMP/FSET for logic high | Internal frequency setting with f = 2.25 MHz | VIN | V | ||||
| VTH_PG | UVP power good threshold voltage; dc level | Rising (%VFB) | 92% | 95% | 98% | ||
| UVP power good threshold voltage; dc level | Falling (%VFB) | 87% | 90% | 93% | |||
| OVP power good threshold; dc level | Rising (%VFB) | 107% | 110% | 113% | |||
| OVP power good threshold; dc level | Falling (%VFB) | 104% | 107% | 111% | |||
| Power good de-glitch time | For a high level to low level transition on power good | 40 | μs | ||||
| VOL_PG | Power good output low voltage | IPG = 2 mA | 0.07 | 0.3 | V | ||
| ILKG_PG | Input leakage current (PG) | VPG = 5 V | 100 | nA | |||
| ISS/TR | SS/TR pin source current | 2.1 | 2.5 | 2.8 | μA | ||
| Tracking gain | VFB/VSS/TR | 1 | |||||
| Tracking offset | Feedback voltage with VSS/TR = 0 V | 17 | mV | ||||
| POWER SWITCH | |||||||
| RDS(ON) | High-side MOSFET ON-resistance | VIN ≥ 5 V | 37 | 60 | mΩ | ||
| RDS(ON) | Low-side MOSFET ON-resistance | VIN ≥ 5 V | 15 | 35 | mΩ | ||
| High-side MOSFET leakage current | VIN = 6 V; V(SW) = 0 V | 30 | μA | ||||
| Low-side MOSFET leakage current | V(SW) = 6 V | 55 | μA | ||||
| SW leakage | V(SW) = 0.6 V; current into SW pin | –0.025 | 30 | μA | |||
| ILIMH | High-side MOSFET current limit | DC value, for TPS62810; VIN = 3 V to 6 V | 4.8 | 5.6 | 6.65 | A | |
| ILIMH | High-side MOSFET current limit | DC value, for TPS62813; VIN = 3 V to 6 V | 3.9 | 4.5 | 5.35 | A | |
| ILIMH | High-side MOSFET current limit | DC value, for TPS62812; VIN = 3 V to 6 V | 2.8 | 3.4 | 4.3 | A | |
| ILIMH | High-side MOSFET current limit | DC value, for TPS62811; VIN = 3 V to 6 V | 2.0 | 2.6 | 3.35 | A | |
| ILIMNEG | Negative valley current limit | DC value | –1.8 | A | |||
| fS | PWM switching frequency range | 1.8 | 2.25 | 4 | MHz | ||
| fS | PWM switching frequency |
With COMP/FSET tied to VIN or GND | 2.025 | 2.25 | 2.475 | MHz | |
| PWM switching frequency tolerance | Using a resistor from COMP/FSET to GND, fs = 1.8 MHz to 4 MHz | –19% | 18% | ||||
| ton,min | Minimum on time of HS FET | TJ = –40°C to 125°C, VIN = 3.3 V | 50 | 75 | ns | ||
| ton,min | Minimum on time of LS FET | VIN = 3.3 V | 30 | ns | |||
| OUTPUT | |||||||
| VFB | Feedback voltage | 0.6 | V | ||||
| ILKG_FB | Input leakage current (FB) | VFB = 0.6 V | 1 | 70 | nA | ||
| VFB | Feedback voltage accuracy | VIN ≥ VOUT + 1 V | PWM mode | –1% | 1% | ||
| VIN ≥ VOUT + 1 V; VOUT ≥ 1.5 V |
PFM mode; Co,eff ≥ 22 μF, L = 0.47 μH |
–1% | 2% | ||||
| 1 V ≤ VOUT < 1.5 V | PFM mode; Co,eff ≥ 47 μF, L = 0.47 μH |
–1% | 2.5% | ||||
| VFB | Feedback voltage accuracy with voltage tracking | VIN ≥ VOUT + 1 V; VSS/TR = 0.3 V |
PWM mode | –1% | 7% | ||
| Load regulation | PWM mode operation | 0.05 | %/A | ||||
| Line regulation | PWM mode operation, IOUT = 1 A, VIN ≥ VOUT + 1 V | 0.02 | %/V | ||||
| Output discharge resistance | 50 | Ω | |||||
| tdelay | Start-up delay time | IOUT = 0 mA, time from EN = high to start switching; VIN applied already | 135 | 250 | 650 | μs | |
| tramp | Ramp time; SS/TR pin open | IOUT = 0 mA, time from first switching pulse until 95% of nominal output voltage; device not in current limit | 100 | 150 | 200 | μs | |