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ZHCSEQ2A February 2016 – February 2016 TPS62480

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RNC|16
- MPQF434

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcseq2a_oa

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Pin Voltage Range⁽²⁾	VIN	-0.3	6	V
	SW1, SW2	-0.3	V_IN+0.3	V
	EN, VSEL, MODE, SS/TR, PG, TG	-0.3	6	V
	FB, RS	-0.3	3	V
Power Good / Thermal Good Sink Current	PG, TG		10	mA
Operating Junction Temperature Range, T_J		-40	150	°C
Storage Temperature Range, T_stg		-65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to network ground terminal.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Supply Voltage Range, V_IN	2.4	5.5	V
Output Voltage Range, V_OUT	0.6	5.5	V
Maximum Output Current, I_OUT	6		A
Operating junction temperature, T_J	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS62480		UNIT
		RNC 16 PINS
		JEDEC with thermal vias⁽²⁾	JEDEC standard
R_θJA	Junction-to-ambient thermal resistance	26.4	56.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	32.2	32.2	°C/W
R_θJB	Junction-to-board thermal resistance	10.2	26.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.9	1.3	°C/W
ψ_JB	Junction-to-board characterization parameter	10.2	26.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	-	-	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) See the Layout section.

6.5 Electrical Characteristics

over operating junction temperature range (T_J = –40°C to 125°C) and V_IN = 2.4 V to 5.5 V. Typical values at V_IN = 3.6 V and T_J = 25°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SUPPLY
V_IN	Input Voltage Range	V_IN rising		2.6		5.5	V
V_IN	Input Voltage Range	V_IN falling		2.4		5.5	V
I_Q	Operating Quiescent Current	EN = High, V_IN≥ 3 V, I_OUT= 0 mA, device not switching, T_J= -40°C to +85°C			23	38	µA
I_Q	Operating Quiescent Current	100% Mode operation			3.5	6.5	mA
I_SD	Shutdown Current	EN = Low (≤ 0.3 V), T_J = -40°C to +85°C			0.5	18.5	µA
V_UVLO	Undervoltage Lockout Threshold	Falling Input Voltage		2.2	2.3	2.4	V
V_UVLO	Undervoltage Lockout Threshold	Hysteresis			200		mV
T_SD	Thermal Shutdown Temperature	PWM Mode, Rising Junction Temperature			160		°C
T_SD	Thermal Shutdown Hysteresis	PWM Mode			10		°C
CONTROL (EN, VSEL, MODE, SS/TR, PG, TG)
V_H	Input Threshold Voltage (EN, VSEL, MODE)	to ensure High Level		1.2			V
V_L	Input Threshold Voltage (EN, VSEL, MODE)	to ensure Low Level				0.4	V
I_LKG(EN)	Input Leakage Current (EN)	EN = V_IN or GND			10	200	nA
I_LKG(MODE)	Input Leakage Current (MODE, VSEL)				10	200	nA
I_SS/TR	SS/TR pin source current			4.7	5.25	5.8	µA
V_TH(TG)	Thermal Good Threshold Temperature	PWM Mode			120		°C
V_TH(TG)	Thermal Good Hysteresis	PWM Mode			10		°C
V_TH(PG)	Power Good Threshold Voltage	Rising (%V_OUT)		93%	96%	99%
V_TH(PG)	Power Good Threshold Voltage	Falling (%V_OUT)		89%	92%	95%
V_L(PG)	Output Low Threshold (PG, TG)	I_PG= -2 mA				0.4	V
I_LKG(PG)	Input Leakage Current (PG)				2	700	nA
I_LKG(TG)	Input Leakage Current (TG)				2	100	nA
t_SS	Internal Soft-Start Time	SS/TR = V_IN or floating			80		µs
t_DELAY	Time from EN rising until start switching			100	200	400	µs
POWER SWITCH
R_DS(ON)	High-Side MOSFET ON-Resistance	V_IN ≥ 3 V	Phase1		36	98	mΩ
	High-Side MOSFET ON-Resistance		Phase2		36	98	mΩ
	Low-Side MOSFET ON-Resistance		Phase1		29	72	mΩ
	Low-Side MOSFET ON-Resistance		Phase2		29	72	mΩ
I_LIM	High-Side MOSFET Current Limit	per phase		4.3	5.0	5.8	A
OUTPUT
V_REF	Internal Reference Voltage				0.6		V
I_LKG(FB)	Input Leakage Current (FB)	EN = High	V_FB= 0.6 V		1	65	nA
I_LKG(RS)	Input Leakage Current (RS)		VSEL = Low, V_RS= 0.6 V		1	65	nA
R_RS	Internal resistance (RS to GND)		VSEL = High, I_RS= 1 mA		10	50	Ω
V_OUT	Output Voltage Range	V_IN ≥ V_OUT		0.6		5.5	V
V_OUT	Feedback Voltage Accuracy	PWM Mode, V_IN≥ V_OUT + 1 V	T_J = –20°C to 85°C	-1%		1%
V_OUT	Feedback Voltage Accuracy	PWM Mode, V_IN≥ V_OUT + 1 V	T_J = –40°C to 125°C	-1.4%		1.3%
V_OUT	Feedback Voltage Accuracy	Power Save Mode, L = 0.47 µH, C_OUT = 4 x 22 µF⁽¹⁾		-1.4%		2.5%
	Output Discharge Current⁽²⁾	EN = Low, V_OUT = 2.5 V			120		mA
	Load Regulation	V_OUT = 1.8 V, PWM mode operation			0.02		%/A
	Line Regulation	2.6 V ≤ V_IN ≤ 5.5 V, V_OUT= 1.8 V, I_OUT= 6 A, PWM mode operation			0.02		%/V

(1) The output voltage accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage ripple.

(2) For detailed information on output discharge see Active Output Discharge.

6.6 Typical Characteristics

Figure 1. Quiescent Current

Figure 3. High-Side Switch Resistance

Figure 2. Shutdown Current

Figure 4. Low-Side Switch Resistance